February 2007
rev 1.4
ASM3P2508A
DC Electrical Characteristics
(Test Condition : All the parameters are measured at room temperature (25°C) , unless otherwise stated)
Parameter
Symbol
Conditions / Description
Min
Typ
Max
Unit
Overall
Supply Current,
VDD =3.3V, FCLK =14.31818MHz,
CL=15pF
Icc
40
27
49
35
60
43
mA
mA
Dynamic
Supply Current,
Static
IDD
VDD = 3.3V, Software Power Down*
All input pins
High-Level Input
VIH
VIL
IIH
VDD=3.3V
VDD=3.3V
2.0
VSS-0.3
-1
-
-
VDD+0.3
0.8
V
Voltage
Low-Level Input
Voltage
V
High-Level Input
Current
µ A
-
1
Low-Level Input
µ A
IIL
-20
-36
-80
Current (pull-up)
Clock Outputs (FOUT1CLK, FOUT2CLK)
High-Level Output
VOH
VOL
VDD= 3.3V, IOH = 20mA
2.5
0
-
-
3.3
0.4
V
V
Voltage
Low-Level Output
Voltage
VDD= 3.3V, IOL = 20mA
ZOH
ZOL
VO=0.5VDD; output driving high
Vo=0.5VDD; output driving low
-
-
29
27
-
-
Output Impedance
Ω
* FOUT1CLK (120MHz) is functional and not loaded
AC Electrical Characteristics
Parameter
Rise Time
Fall Time
Symbol
Conditions/ Description
Min
Typ
Max
Unit
pS
FOUT1CLK
640
440
660
460
680
480
720
520
750
600
800
570
tr
tf
VO = 0.8V to 2.0V; CL = 15pF
VO = 2.0V to 0.8V; CL = 15pF
FOUT2CLK
FOUT1CLK
FOUT2CLK
pS
Clock Duty
Cycle
Ratio of pulse width (as measured from rising edge
tD
45
-
55
%
to next falling edge at 2.5V) to one clock period
Output Frequency =120MHz
Output Frequency =72MHz /48 MHz
-
-
±2.73
±1.78
-
-
Frequency
Deviation
fD
%
On rising edges 500 uS apart at 2.5 V relative to an
-
-
-
-
45
-
-
-
-
ideal clock, PLL B inactive *
Jitter, Long
Term
Tj (LT)
pS
On rising edges 500 uS apart at 2.5 V relative to an
ideal clock, PLL B active *
165
110
390
From rising edge to next rising edge at 2.5 V,
PLL B inactive *
Jitter, peak to
peak
Tj (∆T)
pS
µS
From rising edge to next rising edge at 2.5 V,
PLL B active *
Clock
Output active from power up, RUN Mode via
Software Power Down
Stabilization
Time
tSTB
-
125
-
* CL = 15 pF, Fxin = 14.31818MHz
Peak EMI Reducing Solution
3 of 9
Notice: The information in this document is subject to change without notice.