November 2006
rev 0.3
ASM2P2310A
Timing Requirements
Over recommended ranges of supply voltage and operating free-air temperature
Symbol
Parameter
Test Conditions
VDD = 3 V to 3.6V
VDD = 2.3 V to 2.7V
Min
0
0
Typ
Max
200
170
Unit
fclk
Clock frequency
MHz
Switching Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
VDD = 3.3 V ±0.3 V (See Figure 2)
Symbol
Parameter
Test Conditions
f = 0 MHz to 200 MHz
For circuit load,
see Figure 2.
Min
Typ
Max
Unit
tPLH
CLK to Yn
1.3
2.8
nS
tPHL
tsk(o)
tsk(p)
tsk(pp)
tr
Output skew (Ym to Yn)1(see Figure 4)
Pulse skew (see Figure 5)
Part-to-part skew
Rise time (see Figure 3)
100
250
500
2
pS
pS
pS
V/nS
V/nS
nS
nS
nS
nS
VO = 0.4V to 2V
VO = 2 V to 0.4V
0.7
0.7
0.1
0.1
0.4
0.4
tf
Fall time (see Figure 3)
2
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time,G_high before CLK↓
Disable setup time, G_low before CLK↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
Note: 1 The tsk(o) specification is only valid for equal loading of all outputs
VDD = 2.5 V ±0.2 V (See Figure 2)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
f = 0MHz to 170MHz
For circuit load,
see Figure 2.
tPLH
1.5
3.5
nS
CLK to Yn
tPHL
Output skew (Ym to Yn)1(see Figure 4)
Pulse skew (see Figure 5)
Part-to-part skew
Rise time (see Figure 3)
Fall time (see Figure 3)
Enable setup time,G_high before CLK↓
Disable setup time, G_low before CLK↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
170
400
600
1.4
pS
pS
pS
V/nS
V/nS
nS
nS
nS
nS
tsk(o)
tsk(p)
tsk(pp)
tr
0.5
0.5
0.1
0.1
0.4
0.4
VO = 0.4V to 1.7V
VO = 1.7V to 0.4V
tf
1.4
tsu(en
tsu(dis)
th(en)
th(dis)
Note: 1 The tsk(o) specification is only valid for equal loading of all outputs.
2.5-V TO 3.3-V High-Performance Clock Buffer
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Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
