November 2006
rev 0.3
ASM2P2310A
Function Table
Input
2G
L
L
H
Output
1G
L
H
L
H
CLK
1Y[0:4]
L
2Y[0:4]
L
↓
↓
↓
↓
CLK1
L
L
CLK1
CLK1
H
CLK1
Note: 1 After detecting one negative edge on the CLK input, the output follows the input CLK if the control pin is held high.
Detailed Description
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input
such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the
input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for predictable
operation.
CLK
Gn
Yn
th(en)
tsu(en)
a) Enable Mode
CLK
Gn
Yn
th(dis)
tsu(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
2.5-V TO 3.3-V High-Performance Clock Buffer
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Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
