May 2005
ASM2I99448
rev 0.3
Table 2. PIN CONFIGURATION
Pin#
Pin Name
I/O
Type
Function
4,3
Input
LVPECL
LVPECL Clock Inputs
PCLK, PCLK
2
1
CCLK
Input
Input
LVCMOS Alternative clock signal input
LVCMOS Clock input select
CLK_SEL
5
6
Input
Input
LVCMOS Clock output enable/disable
CLK_STOP
OE
Output enable/disable
LVCMOS
(high–impedance tristate)
31,29,27,25,23,21,19,17,15,13,11,9 Q0 – Q11
Output LVCMOS Clock output
Negative power supply (GND) for
8,12,16,20,24,28,32
GND
Supply Ground
I/O and core.
Positive power supply for I/O and
core. All VCC pins must be
connected to the positive power
supply for correct operation
7,10,14,18,22,26,30
VCC
Supply VCC
Table 3. ABSOLUTE MAXIMUM RATINGS1
Symbol
Parameter
Min
Max
3.9
Unit
V
Supply Voltage
–0.3
–0.3
–0.3
VCC
VIN
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
V
VCC + 0.3
V
VOUT
IIN
VCC + 0.3
±20
mA
mA
°C
±50
125
IOUT
TStor
Storage Temperature Range
–65
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
3 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
