May 2005
ASM2I99448
rev 0.3
Block Diagram
Pin Diagram
VCC
Q0
PCLK
PCLK
24 23
22
21
20
19
18
17
0
1
CLK
Q3
VCC
Q2
25
16
15
14
13
12
11
10
9
GND
Q8
Q1
Q2
STOP
CCLK
26
27
28
29
30
31
32
Q3
VCC
Q4
Q5
Q6
GND
Q1
Q9
ASM2I99448
VCC
VCC
GND
Q10
VCC
CLK_SEL
VCC
Q0
Q7
Q8
SYNC
CLK_STOP
Q9
GND
Q11
1
2
3
4
5
6
7
8
Q10
Q11
VCC
OE
(All input resistors have a value of 25Kꢀ)
Table 1. FUNCTION TABLE
Control
CLK_SEL
OE
Default
0
1
1
1
PECL differential input selected
CCLK input selected
Outputs enabled
Outputs disabled (high-impedance state)1
Outputs synchronously stopped in logic low
state
1
Outputs active
CLK_STOP
Note: 1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
2 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
