January 2006
ASM2P20805A
rev 0.2
Test Circuits and Waveforms
4.6V
VCC
Open
GND
500Ω
VIN
VOUT
Pulse
D.U.T
RL
CL
RT
500Ω
Enable and Disable Time Circuit
VCC
3V
1.25V
0V
INPUT
tPHL1
tPLH1
VIN
VOH
1.25V
VOL
VOUT
OUTPUT 1
OUTPUT 2
Pulse
D.U.T
RL
CL
RT
tSK(O)
tSK(O)
VOH
1.25V
VOL
tPHL2
tPLH2
CL = 15pF Test Circuit
tSK(O)
= | tPLH2 - tPLH1 | or | tPHL2 - tPHL1
Switch Position
Test
Test Conditions
Symbol
VCC = 2.5V ±0.2V
Unit
pF
Switch
CL
RT
RL
15
Disable Low
Enable Low
4.6V
ZOUT of pulse generator
33
Ω
Ω
Disable High
Enable High
GND
tR / tF
1 (0V to 2.5V or 2.5V to 0V)
nS
Definitions:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
t
R / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
2.5V CMOS Dual 1-To-5 Clock Driver
6 of 12
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
