OX16PCI958 DATA SHEET
OXFORD SEMICONDUCTOR LTD.
Table 5 Register Offsets
BAR
Internal address
Use
BAR0, 1 00h – 19h
30h
PCI setup registers, as described in section 3.4.
EEPROM-control register
31h
34h
Power-management control register
UART interrupt status
35h
40h
41h
42h
4Ch
UART-enable register
UART IO bank switching/rotation
SISR enable register
UART configuration
50h
Global UART clock pre-divider
UART 0 registers 0-7
UART 1 registers 0-7
UART 2 registers 0-7
UART 3 registers 0-7
UART 4 registers 0-7
UART 5 registers 0-7
UART 6 registers 0-7
UART 7 registers 0-7
SISR, if SISR enabled
UART 0 registers 8-9, if SISR not enabled
UART 1 registers 8-9
UART 2 registers 8-9
UART 3 registers 8-9
UART 4 registers 8-9
UART 5 registers 8-9
UART 6 registers 8-9
UART 7 registers 8-9
RFU
BAR2,4 80h-87h
88h-8Fh
90h-97h
98h-9Fh
A0h-A7h
A8h-AFh
B0h-B7h
B8h-BFh
BAR3,5 C0h
C0h-C1h
C2h-C3h
C4h-C5h
C6h-C7h
C8h-C9h
CAh-CBh
CCh-CDh
CEh-CFh
other
Notes:
•
Writes to undefined internal addresses are ignored, and reads from undefined internal addresses
return zero
•
For shared address ranges, the SISR takes priority over the UARTs
DS-0022 Nov 05
External—Free Release
Page 8
OXFORD [ OXFORD SEMICONDUCTOR ]
