OXFORD SEMICONDUCTOR LTD.
OX16PCI958 DATA SHEET
3. PCI
INTERFACE
The PCI interface conforms to revisions 2.1, 2.2, 2.3 and 3.0 of the PCI Specification, and version 1.1
of the PCI Power Management Specification.
Six base address registers are implemented in the OXPCI958:
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BAR0—128-byte memory-mapped region
BAR1—128-byte I/O-mapped region
BAR2—64-byte I/O-mapped region
BAR3—16-byte I/O-mapped region
BAR4—64-byte memory-mapped region
BAR5—16-byte memory-mapped region
All memory regions are in 32-bit address space, and are marked as non-prefetchable.
3.1.
Internal Address Map
The internal address map is referenced by the EEPROM to configure the UARTs. Table 4 shows how
PCI accesses are mapped to internal addresses:
Table 4 PCI Address Mapping
PCI side
BAR0, 1
local side
configuration
local functions
local functions
PCI bridge configuration
EEPROM control, power management
UART, SISR
UARTs
SISR
00h to 2Fh
30h to 3Fh
40h to 7Fh
80h to BFh
C0h to CFh
BAR2, 4
BAR3, 5
Notes:
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Addresses in the range 40h-7Fh are aliased with a period of 32, i.e., address bit 5 is not decoded
in this range
Addresses in the range C0h-FFh are aliased with a period of 16, i.e., address bits 5:4 are not
decoded in this range. For example, if BAR4 is configured as C8000400h, a memory access at
C8000413h, which is BAR4+13h, would access internal address 80h+13h = 93h
The serial EEPROM reader can access any internal address
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Table 5 lists the PCI register offsets.
DS-0022 Nov 05
External—Free Release
Page 7
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