OX16PCI958 DATA SHEET
OXFORD SEMICONDUCTOR LTD.
Power-Management Control Register
Global UART Clock Pre-Divider
Each two-bit group represents a power-
management level range, as shown in Table 7,
defining whether an element is disabled, which
is shown in Table 8.
This register sets a pre-division value for all
the internal UARTs.
Bit 5—One of the clock pre-division factors,
see Table 9
Table 7 Power Management Group
Bit 2—One of the clock pre-division factors,
see Table 9
Field (Bits)
PM_DRIVER
PM_LCLK
PM_OSC
Control Measure
After a reset, this register is set to F6h, giving
a divide-by-8 clock setting for all UARTs. For
the standard 14.7456 MHz external crystal,
this gives a 1.8432 MHz effective clock to the
UARTs.
driver_en output deasserted
Local-side clock gated off
Local-side oscillator disabled
Table 8 Element Disabling
For backwards compatibility, write only one of
the four values in Table 9 to bits 5 and 2:
Value
Description
0 0
0 1
1 0
1 1
Never disabled
Table 9 Clock Pre-Division Values
Disabled in D1, D2 & D3
Disabled in D2 and D3
Disabled in D3 only
Value
F6h
F2h
D6h
D2h
Divisor
8
4
2
1
This register is set to 00h on a PCI reset.
UART Interrupt State
The above register settings are recommended
for backwards compatibility, but Table 10
shows how the actual control logic operates.
Each bit in this read-only register reports the
interrupt status of the corresponding internal
UART.
Table 10 Clock Division Logic
UART Enable
GCS1
GCS0
Division
1
1
0
0
1
0
1
0
8
4
2
1
Each bit in this register enables the
corresponding internal UART to be accessed
on the internal bus, by either the PCI interface
or the EEPROM reader.
SISR Enable
Bit 7 must be set to enable access to the
shared interrupt status register (SISR).
This register is set to 80h on a PCI reset.
UART Configuration
Bit 5 must be set to binary 1 to ensure correct
operation of the UART
DS-0022 Nov 05
External—Free Release
Page 10
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