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ML87V2107TB 参数 Datasheet PDF下载

ML87V2107TB图片预览
型号: ML87V2107TB
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100]
分类和应用: 商用集成电路
文件页数/大小: 152 页 / 739 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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FEDL87V2107-01  
OKI Semiconductor  
ML87V2107  
Termination of  
unused pin  
No.  
Symbol  
I/O  
Pad Remarks  
Pin Description  
Mode setting pin bit 1  
Schmitt  
Not used or  
connected to GND  
32  
33  
34  
MODE1  
N.C.  
I
I
(Equivalent to internal register HMD[0])  
pull-down 50k  
Unused pin  
Not used  
Schmitt  
Mode setting pin bit 2  
(Equivalent to internal register DISEL[0])  
Clock output (I2C-bus control possible)  
Not used or  
connected to GND  
MODE2  
pull-down 50k  
35  
36  
37  
CLKO  
VDD  
O
Not used  
3.3 V power supply  
X
X
VSS  
Ground  
Crystal oscillator input  
(24.545454/27/28.63636/29.5 MHz)  
38  
XTI  
I
WOSC8FLHM  
Crystal oscillator output  
(24.545454/27/28.63636/29.5 MHz)  
3.3 V power supply  
39  
40  
XTO  
VDD  
O
Not used  
X
DNR mode setting input pin  
0: Memory output noise reduction mode  
1: Direct noise reduction mode  
Asynchronous/synchronous generation setting  
input pin  
0: IVS reset synchronous generation mode  
1: Asynchronous/synchronous generation  
mode  
Schmitt  
Not used or  
connected to GND  
41  
DNR  
pull-down 50k  
Schmitt  
pull-down 50k  
Not used or  
connected to GND  
42  
43  
44  
ASYNC  
N.C.  
N.C.  
Not used  
Internal Sync. signal generation mode setting  
input pin  
0: OVS/OHS input mode  
1: OVS/OHS output mode (internal Sync. signal  
generation)  
Schmitt  
pull-down 50k  
Not used or  
connected to GND  
INT  
45  
46  
OHS  
OVS  
I/O  
I/O  
pull-down 50k Horizontal Sync. signal output pin  
pull-down 50k Vertical Sync. signal output pin  
Not used  
Not used  
Data output horizontal reference signal output  
pin  
Ground  
47  
48  
HREF  
VSS  
O
Not used  
X
Asynchronous/synchronous generation TRG  
49  
TRG  
I/O  
pull-down 50k input/output pin  
Not used  
Output at master Input at slave  
50  
51  
VDD  
3.3 V power supply  
X
Chrominance signal output pin bit 0 (LSB)  
SCAN test data input pin bit 0 (TEST6=1)  
Chrominance signal output pin bit 1  
SCAN test data input pin bit 1 (TEST6=1)  
Chrominance signal output pin bit 2  
SCAN test data input pin bit 2 (TEST6=1)  
Chrominance signal output pin bit 3  
SCAN test data input pin bit 3 (TEST6=1)  
CO0  
I/O  
pull-down 50k  
pull-down 50k  
pull-down 50k  
pull-down 50k  
Not used  
52  
53  
CO1  
CO2  
I/O  
I/O  
Not used  
Not used  
54  
55  
56  
CO3  
VSS  
I/O  
Not used  
X
Ground  
Chrominance signal output pin bit 4  
SCAN test data input pin bit 4 (TEST6=1)  
Chrominance signal output pin bit 5  
SCAN test data input pin bit 5 (TEST6=1)  
Chrominance signal output pin bit 6  
SCAN test data input pin bit 6 (TEST6=1)  
Chrominance signal output pin bit 7 (MSB)  
SCAN test data input pin bit 7 (TEST6=1)  
CO4  
I/O  
pull-down 50k  
pull-down 50k  
pull-down 50k  
pull-down 50k  
Not used  
57  
58  
59  
CO5  
CO6  
CO7  
I/O  
I/O  
I/O  
Not used  
Not used  
Not used  
60  
61  
VDD  
3.3 V power supply  
X
X
OCLK  
I/O  
Output system clock input/output pin  
6/152