FEDL87V2107-01
OKI Semiconductor
ML87V2107
PIN DESCRIPTIONS
Termination of
unused pin
No.
Symbol
I/O
Pad Remarks
Pin Description
1
2
N.C.
VSS
—
—
Unused pin
Ground
Not used
X
Schmitt(IN)/
OpenDrain(OUT)
Schmitt
3
4
5
SDA
SCL
I/O
I2C-bus data pin
I2C-bus clock pin
X
I
I
X
Schmitt
Not used or
connected to GND
SLA1
Slave address setting pin bit 1
Slave address setting pin bit 2
pull-down 50k
Schmitt
Not used or
connected to GND
6
SLA2
I
pull-down 50k
7
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
VDD
ICLK
VSS
I
I
Luminance signal input pin bit 7 (MSB)
Luminance signal input pin bit 6
Luminance signal input pin bit 5
Luminance signal input pin bit 4
Luminance signal input pin bit 3
Luminance signal input pin bit 2
Luminance signal input pin bit 1
Luminance signal input pin bit 0 (LSB)
3.3 V power supply
X
X
X
X
X
X
X
X
X
X
X
8
9
I
10
11
12
13
14
15
16
17
I
I
I
I
I
—
I
Input system clock pin
—
Ground
Not used or
connected to GND
18
19
20
21
22
23
24
CI7
CI6
CI5
CI4
CI3
CI2
CI1
I
I
I
I
I
I
I
pull-down 50k Chrominance signal input pin bit 7 (MSB)
pull-down 50k Chrominance signal input pin bit 6
pull-down 50k Chrominance signal input pin bit 5
pull-down 50k Chrominance signal input pin bit 4
pull-down 50k Chrominance signal input pin bit 3
pull-down 50k Chrominance signal input pin bit 2
pull-down 50k Chrominance signal input pin bit 1
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
25
26
CI0
VDD
I
pull-down 50k Chrominance signal input pin bit 0 (LSB)
3.3 V power supply
—
X
Clock select signal for crystal oscillation output
0: No crystal oscillation clock (OCLK input)
1: Crystal oscillation clock (OCLK output)
Schmitt
Not used or
connected to GND
27
XTSL
I
pull-down 50k
28
29
VSS
IVS
—
I
Ground
X
Schmitt
Not used or
connected to GND
Input system vertical Sync. signal input pin
pull-down 50k
Schmitt
Not used or
connected to GND
30
31
IHS
I
I
Input system horizontal Sync. signal input pin
pull-down 50k
Schmitt
Mode setting pin bit 0
(Equivalent to internal register VMD[0])
Not used or
connected to GND
MODE0
pull-down 50k
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