FEDL86V7666-01
OKI Semiconductor
ML86V7666
Pin
85
86
Symbol
MODE [3]
MODE [2]
I/O
I
87
88
MODE [1]
MODE [0]
I
89
|
91
GAINS [2]
|
GAINS [0]
I
92
|
94
INS [2]
|
INS [0]
I
95
96
97
98
99
100
DV
DD
DGND
PV
DD
VREF
LPF
PGND
—
—
—
O
I
—
Description
Output mode external setting pins "0" when not used.
Valid when register $00/MRA[0] = 0 (default).
MODE [3:2]
00: ITU-R BT.656 (10-bit Y/CbCr + SAV, EAV, blank)
01: 10-bit Y/CbCr (10-bit Y/CbCr multiplexed data)
10: 20-bit Y/CbCr (10-bit Y + 10-bit CbCr demultiplexed data)
11: 24-bit RGB/YCbCr (RGB or YCbCr 8+8+8-bit demultiplexed
data)
Register $10/CHRCB[1] = 0: 24-bit RGB, 1: 24-bit YCbCr
Operation mode external setting pins "0" when not used.
Valid when register $00/MRA[0] = 0 (default).
MODE [1] 0: NTSC, 1: PAL
Invalid when register $02/MRC[7] = 1 (NTSC/PAL automatic
recognition).
MODE [0] 0: ITU-R BT. 601, 1: Square Pixel
NTSC 4fsc can be set by register $00/MRA[5:3] only.
Amplifier gain external setting pins "0" when not used.
Valid when external pin 82 M[1]=0.
GAINS [2:0] Gain value (x times)
[000]
0.55
[001]
0.70
[010]
0.93
[011]
1.21
[100]
1.60
[101]
2.09
[110]
2.65
[111]
3.45
Input pin switch external setting pins "0" when not used.
Valid when external pin 82 M[1]=0.
INS[2:0] Input pin
[000]
VIN1(Pin 3) Composite-1
[001]
VIN2(Pin 4) Composite-2
[010]
VIN3(Pin 5) Composite-3
[011]
VIN4(Pin 6) Composite-4
[100]
VIN5(Pin 7) Composite-5
[101]
VIN1(Pin 3) Y-1
VIN5(Pin 7) C-1
[110]
VIN2(Pin 4) Y-2
VIN6(Pin 8) C-2
[111]
Prohibited setting (ADC enters sleep mode)
Digital power supply
Digital ground
PLL power supply
Center frequency setting pin "0" when not used.
Analog PLL loop filter connection pin "0" when not used.
Refer to the sample circuits provided in the User's Manual.
PLL ground
*) Leave open when not used.
Connect a pull-up resistor in High-Z output mode .
8/36
OKI [ OKI ELECTRONIC COMPONETS ]
