FEDL86V7666-01
OKI Semiconductor
ML86V7666
Pin
45
46
Symbol
C[1]/B[7]
C[0]/B[6]
I/O
O
47
|
50
B [5]
|
B [2]
O
51
52
53
54
DVDD
DGND
Y [0]/B [1]
Y [1]/B [0]
—
—
O
Description
Data output C[1]-C[0]LSB or B[7]MSB-B[6] *)
ITU-R BT.656 mode: Hi-Z
10-bit Y/CbCr mode: Hi-Z
20-bit Y/CbCr mode: CbCr lower 2-bit output
24-bit RGB mode: B upper 2-bit output
24-bit component mode: Cb upper 2-bit output
The output mode is set by pins 85 and 86, or register
$00/MRA[7:6].
Data output B[5] - B[2] *)
ITU-R BT.656 mode: Hi-Z
10-bit Y/CbCr mode: Hi-Z
20-bit Y/CbCr mode: Hi-Z
24-bit RGB mode: B intermediate 4-bit output
24-bit component mode: Cb intermediate 4-bit output
For upper 2 bits, pins 45 and 46 are used, for lower 2 bits, pins 53
and 54 are used.
The output mode is set by pins 85 and 86, or register
$00/MRA[7:6].
Digital power supply
Digital ground
Data output Y[1]-Y[0]LSB or B[1]-B[0]LSB *)
ITU-R BT.656 mode: YCbCr lower 2-bit data output
10-bit Y/CbCr mode: YCbCr lower 2-bit data output
20-bit Y/CbCr mode: Y lower 2-bit data output
24-bit RGB mode: B lower 2-bit data output
24-bit component mode: Cb lower 2-bit data output
The output mode is set by pins 85 and 86, or register
$00/MRA[7:6].
Data output Y[9]: MSB - Y[2] *)
ITU-R BT.656 mode: YCbCr upper 8-bit data output
10-bit Y/CbCr mode: YCbCr upper 8-bit data output
20-bit Y/CbCr mode: Y upper 8-bit data output
24-bit RGB mode: G 8-bit data output
24-bit component mode: Y 8-bit data output
When performing 10-bit output in BT.656 / (Y/CbCr) output mode,
add pins 53 and 54.
The output mode is set by pins 85 and 86, or register
$00/MRA[7:6].
Digital power supply
Digital ground
Horizontal valid pixel timing signal output *)
"H" is output for horizontal valid data section.
Vertical valid line timing signal output *)
"H" is output for vertical valid data section.
Vertical sync signal output (V sync) *)
Horizontal sync signal output (H sync) *)
Field display output *)
"H" is output for ODD field section.
Pixel clock output
Double-speed clock mode (Pin 75 =0)
One half of system clock frequency is output.
Normal clock mode (Pin 75 = 1)
The same frequency as system clock frequency is output.
Operating clock output
The same frequency as the Operating mode clock frequency is
output.
Digital power supply
Digital ground
55
|
62
Y [2]
|
Y [9]
O
63
64
65
66
67
68
69
70
DVDD
DGND
HVALID
VVALID
VSYNC_L
HSYNC_L
ODD/EVEN
CLKXO
—
—
O
O
O
O
O
O
71
CLKX2O
O
72
73
DVDD
DGND
—
—
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