FEDL86V7666-01
OKI Semiconductor
ML86V7666
Pin
74
Symbol
CLKX2
I/O
I
Description
System clock input
Input a fixed clock or a PLL reference clock.
Fixed clock (Pin 76 = 0)
Normal clock
(Pin 75 = 1)
Operating mode
NTSC ITU-R BT. 601
NTSC Square Pixel
NTSC 4Fsc
PAL ITU-R BT. 601
PAL Square Pixel
13.5 MHz
12.272727 MHz
14.31818 MHz
13.5 MHz
14.75 MHz
Double-speed clock
(Pin 75 = 0)
27 MHz
24.545454 MHz
28.63636 MHz
27 MHz
29.5 MHz
75
CLKSEL
I
76
77
PLLSEL
VHVAL
/SCALW
I
O
78
CSYNC
/SCALR
O
79
STATUS2
O
80
STATUS1
O
81
M [2]
I
82
M [1]
I
83
84
M [0]
DGND
I
—
PLL reference clock (Pin 76 = 1)
Register $1F/PLLR[0] 0:32 MHz(default) 1: 25 MHz
Double-speed clock select pin
0: Double-speed clock mode 1: Normal clock mode
When the double-speed clock mode is set, input a doubled
frequency to the system clock.
When Pin 76 PLLSEL = 1 (PLL clock mode), set to 0 to select the
double-speed clock mode.
PLL clock select pin
0: Fixed clock 1: PLL clock
Register $1A/SCR[7:6] = 00 (When scaling is not used.)
VHVAL (VVALID
∧
HVALID) output
Register $1A/SCR[7:6] = 01-11 (scaling mode)
External memory writing control signal output
Register $18/OMRD[5:4] = 01-11 (QVGA mode)
QVGA clock is output.
Register $1A/SCR[7:6] = 00 (When scaling is not used.)
CSYNC (Composite SYNC) output
Register $1A/SCR[7:6] = 01-11 (scaling mode)
External memory read control signal output
Status signal output
Selected by register $15/OMRA[0].
OMR[0]:0 NTSC-PAL recognition output (default)
0: NTSC 1: PAL
OMR[0]:1 HLOCK sync detection output
0: Non-detection 1: Detection
Status signal output
Selected by register $15/OMRA[1]
OMR[1]: 0 FIFO overflow detection output (default)
0: Non-detection 1: Detection
OMR[1]: 1 PLL sync detection output
I2C-bus slave address select "0" when not used.
0: 1000 001X (X: 0 = Write, 1 = Read)
1: 1000 011X (X: 0 = Write, 1 = Reed)
Amplifier gain setting and input pin switch setting control select pin
0: External pin mode
Amplifier gain setting: Pins 89 to 91 GAINS[2:0] are used
Input pin setting: Pins 92 to 94 INS[2:0]) are used
1: Register mode
Amplifier gain setting: Register $1E/ADC2[6:4]
Input pin setting: Register $1D/ADC1[2:0]
The internal register setting is invalid when the external pin mode is
set.
Not used. Fixed at "0".
Digital ground
7/36
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