FEDL70Q5110LA-01
OKI Semiconductor
ML70Q5110LA
µPLAT_SIO I/F
Internal
Initial
Value
Pin
Placement
Pin Name
Direction
Description
Pull Up/Down
UTXD
URXD
O
I
—
—
H
N2
L3
Serial data output (Pin shared with GPIO3)
Serial data input (Pin shared with GPIO2)
—
GPIO I/F
Internal
Initial
Value
Pin
Placement
Pin Name
Direction
I/O
Description
Pull Up/Down
Parallel I/O data
GPIO[15:0]
—
—
[*3]
During initialization: input
JTAG I/F
Internal
Pull Up/Down
Pull down
—
Initial
Value
Pin
Placement
Pin Name
Direction
Description
TDI
TDO
TRST
TMS
TCK
I
O
I
—
L
H4
H2
Serial data input
Serial data output
Reset pin
Pull down
Pull down
Pull down
—
—
—
C13
B12
B13
I
Mode setting pin
Serial data clock
I
PCM I/F
Internal
Pull Up/Down
—
Initial
Value
Pin
Placement
Pin Name
Direction
Description
PCMOUT
PCMIN
O
I
L
G2
G4
PCM data output
PCM data input
Pull down
—
PCM sync signal (8 kHz)
PCMSYNC
PCMCLK
I/O
I/O
Pull down
Pull down
—
—
H3
G3
During initialization: input
(can be switched by an internal register)
PCM clock (64 kHz/128 kHz)
During initialization: input
(can be switched by an internal register)
[*3] CIO15: H1 GPIO15/SOUT (UART I/F)
CIO14: J4 GPIO14/SIN (UART I/F)
CIO13: K2 GPIO13/DCD (UART I/F)
CIO12: J1
CIO11: J3
GPIO12/RTS (UART I/F)
GPIO11/CTS (UART I/F)
CIO10: K3 GPIO10/DSR (UART I/F)
CIO9: K1 GPIO9/DTR (UART I/F)
CIO8: L2
CIO7: K4 GPIO7/STXD (SIO I/F)
CIO6: L1 GPIO6/SRXD (SIO I/F)
GPIO8/RI (UART I/F)
CIO5: M2 GPIO5/STXDCLK (SIO I/F)
CIO4: M1 GPIO4/SRXDCLK (SIO I/F)
CIO3: N2 GPIO3/UTXD (µPLAT_SIO I/F)
CIO2: L3
CIO1: N3 GPIO1
CIO0: L4 GPIO0
GPIO2/URXD (µPLAT_SIO I/F)
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OKI [ OKI ELECTRONIC COMPONETS ]
