FEDL70Q5110LA-01
OKI Semiconductor
CLK and Configuration
Pin Name
SCLK
XCLK
SCLKSEL
Direction
I
I
I
Internal
Pull Up/Down
—
—
Pull down
Initial
Value
—
—
—
Pin
Placement
D13
D11
B10
ML70Q5110LA
Description
Master clock (12, 13 or 16 MHz) input pin
(Power level: CMOS level)
User clock input pin
System clock select pin
L: Select CLK divided by internal PLL
H: Select XCLK input signal
Master clock select pin
SCLKFSEL[1:0] = “00” : 12 MHz
“01” : 13 MHz
“10” : 16 MHz
“11” : Forbidden
Hardware reset pin (Reset = L)
Hardware reset pin (Reset = L), Output
BANK0 region bit width select pin
L: 8-bit
H: 16-bit
REMAP select pin during boot up
REMAP[1:0] = “00” Forbidden
“01” Stacked Flash ROM
“10” External
MCS1
device
“11” External
MCS0
device
SCLKFSEL0
SCLKFSEL1
RESET
RESET_OUT
BBWSEL
I
I
I
O
I
Pull down
Pull down
—
—
Pull down
—
—
—
—
—
A9
D9
D5
B9
B8
REMAP0
REMAP1
I
I
—
—
—
—
D10
F11
Memory I/F
Pin Name
MA[19:0]
MD[15:0]
MWE
MRE
MCS0
MCS1
MBS0
MBS1
MOE0
MOE1
Direction
O
I/O
O
O
O
O
O
O
O
O
Internal
Pull Up/Down
—
Pull up
—
—
—
—
—
—
—
—
Initial
Value
L
—
H
H
H
H
H
H
H
H
Pin
Placement
[*1]
[*2]
B4
A5
C4
C5
G10
H10
G13
G11
Description
External address bus
External data bus
External write enable signal output
External read enable signal output
External space 0 chip select
External space 1 chip select
External lower byte select
External upper byte select
External
MCS0
device output enable
(MCS0 and
MRE
OR output)
External
MCS1
device output enable
(MCS1 and
MRE
OR output)
[*1]
MA19: M3; MA18: N4; MA17: L5; MA16: M4; MA15: K5; MA14: M5
MA13: N6; MA12: M6; MA11: K6; MA10: M7; MA9: L7;
MA8: N7;
MA6: K8;
MA5: M9; MA4: N8; MA3: K9;
MA2: M10; MA1: N9;
MA7: L8
MA0: L9
[*2]
MD15: N10; MD14: M11; MD13: K10; MD12: N11; MD11: M12; MD10: M13
MD9: L11; MD8: L13; MD7: K11; MD6: L12; MD5: K13; MD4: J11; MD3: K12;
MD2: J13; MD1: J10; MD0: H12
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