Preliminary
ML696201 and ML69Q6203
Pin Descriptions (Continued)
Primary/
Symbol
I/O
I
Description
Secondary
TDI
This pin is used during debugging. Normally set this input High
—
—
—
TDO
RTCK
O
O
This pin is used during debugging. Normally, do not connect this pin to any trace
This pin is used during debugging. Normally, do not connect this pin to any trace
External Bus Address and Data
XA [23:1]
O
Address of the bus that connects external RAM, external ROM, external IO and external DRAM
Data bus that connects external RAM, external ROM, external IO and external DRAM
Secondary
Secondary
XD [15:0]
I/O
External Bus Controls Signal
XOE_N
O
O
O
O
O
O
O
O
O
O
I
External memory access read enable, Active-Low
External memory access write enable, Active-Low
External ROM chip select, Active-Low
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
XWE_N
XROMCS_N
XRAMCS_N
XBS1_N
External RAM chip select, Active-Low
External memory byte select (MSB), Active-Low
External memory byte select (LSB), Active-Low
I/O bank 1, chip select 1, Active-Low
XBS0_N
XIOCS11_N
XIOCS10_N
XIOCS01_N
XIOCS00_N
XWAIT [1:0]
I/O bank 1, chip select 0, Active-Low
I/O bank 0, chip select 1, Active-Low
I/O bank 0, chip select 0, Active-Low
Wait signal for I/O bank 0/1.A device slower than the register set value can be connected by inputting this signal (wait
when 1).
Secondary
XSYSCLK
O
AHB clock for external bus
Secondary
External Bus Control Signals (DRAM)
XSDCS_N
XCAS_N
XRAS_N
XSDCLK
XSDCKE
XDQM1
O
SDRAM chip select, Active-Low
Column address strobe (SDRAM), Active-Low
Row address strobe (SDRAM), Active-Low
Clock for SDRAM
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
O
O
O
O
O
O
Clock enable (SDRAM)
Input/output mask (MSB)
XDQM0
Input/output mask (LSB)
DMA Control
DREQ
I
DMA request signal.This signal is used if the DREQ type is set by the DMA controller.
Secondary
Secondary
DREQCLR
O
DREQ signal clear request.
The DMA device turns off the DREQ signal when this signal is output.
TCOUT
O
This signal notifies the DAM device that the last transfer has been started.
Secondary
General-Purpose I/O Port
PIOA[15:0]
I/O
I/O
I/O
I/O
I/O
This is a general-purpose port. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
Primary
Primary
Primary
Primary
Primary
PIOB[15:0]
PIOC[15:0]
PIOD [15:0]
PIOE[15:0]
This is a general-purpose port. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
This is a general-purpose port.. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
This is a general-purpose port.. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
This is a general-purpose port.
PIOE[15] is 5-V tolerant.
PIOE[15:12] can be used as IRQ (interrupt requests)
PIOF[6:0]
I/O
This is a general-purpose port.. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
Primary
µPLAT-SIO/UART
Oki Semiconductor • 9
OKI [ OKI ELECTRONIC COMPONETS ]
