ML67Q4050/Q4060 Series
Pin Configuration
Figure 2. 84-Pin Plastic LFBGA
A
GND
B
NC
C
NC
D
VDD_IO
E
PB1/
/RX0
F
PE4/
SD
G
PF2/
TIMER2/
CTS1
H
PF5/
TIMER5/
EXINT5
J
NC
K
VDD_CORE
10
10
9
PB3/
RX1/
EXINT1
NC
VDD_CORE
PB0/
TX0
BOOT0/
PE3/
MCLK
PF[1[/
TIMER1/
RTS0
PF4/
TIMER4/
EXINT4
GND
GND
NC
9
VDD_IO
8
PB4/
SCL/
TXD
PB5/
SDA/
RXD
GND
PB2/
TX1/
EFIQ_N
PF0/
TIMER0/
CTS0
PF3/
TIMER3/
RTS1
VDD_IO
PC0/
MISO0/
DSR0
BOOTCLK/
PD5
8
PE1
PE0
GND
7
PC1/
MOSI0/
DTR0
PC2/
SCK0/
RI0
VDD_IO
7
VDD_IO
GND
PE2
6
ML67Q4060/61
84-Pin LFBGA
(TOP VIEW)
PC4/
MISO1/
DSR1
PC5/
MOSI1/
DTR1
PC3/
SSN0/
DCD0
6
5
PD2/
AIN2
PD0/
AIN0/
EXINT2
PD1/
AIN1/
EXINT3
GND
GND
RESET_N
5
TEST2
4
PD3/
AN3
TEST1
PC6/
SCK1/
RI1
PC7/
SSN1/
DCD1
RSTOUT_N/PA6/
MCLK
4
NC
GND
GND_PLL
RTCCLK_N
GND
3
GND_PLL
VDD_PLL
GND
TCK/
PA0
TDO/
PA3
VDD_IO
PE5/
WS
BS/
PD4
3
SYSCLK_N
2
NC
NC
TDI/
PA2
NTRST/
PA4
VDD_CORE
PE6/
SCK
2
VDD_CORE
VDD_IO
VDD_PLL
RTCCLK_P
SYSCLK_P
1
A
B
C
D
E
TMS/
PA1
VDD_IO
JTAGE/
PA5
NC
GND
1
J
K
F
G
H
NOTES:
1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See
Table for details.
2. NC balls can be connected to VDD_IO or GND.
6
• Oki Semiconductor
June 2006, Rev 1.2
OKI [ OKI ELECTRONIC COMPONETS ]
