ML67Q4050/Q4060 Series
FUNCTIONAL DESCRIPTION
• SPI
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Two channels of full duplex serial-parallel Interface.
Selectable Master/Slave
Independent 16 entry x 16-bit FIFOs
Built-in Baud-rate generator
Support 8-bit width and 16-bit width transfers
Supports DMA operation
• Power Management
- Low-power mode
- HALT mode: Stop the clock supply to CPU and other key components
- STOP mode: Stop the clock supply to CPU and all peripherals except
RTC
- Control the clock supply to each peripherals
- Clock change is dynamically possible in the division ratio of clock input
frequency.
• CLOCK
- Main clock oscillator is 33.33 MHz (Max)
- RTC clock oscillator is 32.768 kHz Clock
- Ring Oscillator
• ML67Q4050/51 Package
- 144-pin LQFP (LQFP144-P-2020-0.50-ZK)
• ML67Q4060/61 Packages
- 64-pin WCSP (P-VFBGA64-5.09x4.84-0.50-W)
– Occupies less than 25 square millimeters
- 64-pin TQFP (TQFP64-P-1010-0.50-K)
- 84-pin LFBGA (P-LFBGA84-0909-0.80)
• RTC
- One second generated from 32.768 kHz
- Built-in 32-bit counter with one second clock
- Interrupt on 32-bit comparison
4
• Oki Semiconductor
June 2006, Rev 1.2
OKI [ OKI ELECTRONIC COMPONETS ]
