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ML67Q4003LA 参数 Datasheet PDF下载

ML67Q4003LA图片预览
型号: ML67Q4003LA
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 19 页 / 645 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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ML674001/ML67Q4002/ML67Q4003  
Pulse Width Modulation  
Built-In Flash ROM Programming  
This MCU contains two channels of Pulse Width Modulation (PWM) function  
which can change the duty cycle of a waveform with a constant period. The  
PWM output resolution is 16 bits for each channel.  
The robust features of the flash permit simple and optimized programming of  
the flash-ROM.  
1. There are three methods for programming the FLASH-ROM  
- Programming via the JTAG interface  
- Programming using boot mode  
Boot mode is used by the host to download data to the FLASH ROM via  
the UART interface.  
A/D Converter  
Successive approximation type A/D converter.  
1. 10 bits x 4 channels  
A program stored in the on-chip boot ROM is used to transfer the  
incoming serial data on the UART interface to the internal Flash ROM.  
- Programming via a user application running from external memory  
Internal flash can be programmed by executing a user flash program-  
ming application from external memory.  
2. Sample and hold function  
3. Scan mode and select mode are supported  
4. Interrupt is generated after completion of conversion.  
5. Conversion time: 5 µs (min).  
2. Single power source for reading and programming of FLASH: 3.0V to  
3.6V  
Power Management  
HALT, STANDBY and clock gear clock control functions are supported as  
power save functions.  
3. Programming units: 2 bytes  
4. Selectable erasing size  
1. HALT mode  
- Sector erase: 2 KBytes/sector  
- Block erase: 64 KBytes/block  
- Chip erase: All memory cell  
HALT object  
- CPU, internal RAM, AHB bus control  
HALT mode setting: Set by the system control register.  
Exit HALT mode due to: Reset, interrupt  
5. Word program time: 20 µsec (2 bytes)  
6. Sector/block erase time: 25 msec  
7. Chip erase time: 100 msec  
8. Write protection  
2. STANDBY mode  
Stops the clock for the entire device.  
STANDBY mode setting: Specified by the system control register.  
Exit STANDBY mode due to: Reset, external interrupt (other than EFIQ_N)  
- Block protect: top address 8Kwords can be protected  
- Chip protect: all words can be protected  
3. Clock gear  
The MCU has two clock systems, HCLK and CCLK. Configure HCLK  
and CCLK frequency.  
HCLK: CPU, bus control, synchronous serial interface, I2C.  
CCLK: Timers, PWM SIO, AD converter, etc.  
9. Number of commands: 9  
10. Highly reliable read/program  
- Sector programming: 1,000 times  
- Data hold period: 10 years  
4. Clock control by each function unit  
AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), SIO, SSIO,  
I2C.  
April 2004, Rev 2.0  
Oki Semiconductor • 5  
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