ML674001/ML67Q4002/ML67Q4003
Direct Memory Access Controller (DMAC)
External Memory Controller
Two-channel direct memory access controller (DMAC) which transfers data
between memory and memory, between I/O and memory, and between I/O
and I/O.
Controls access of externally connected devices such as ROM (FLASH), SRAM,
SDRAM (EDO DRAM), I/O devices and external FLASH memory.
1. ROM (FLASH) access function: 1 bank (supports up to 16 MBytes)
1. Number of
channels:
2 channels
Fixed mode:
Roundrobin:
Supports 16-bit devices
Supports FLASH memory: Byte write (can be written only by IF equivalent
to SRAM).
In ML67Q4002/4003, control internal FLASH access.
Configurable access timing.
2. Channel priority
level:
Channel priority level is always
fixed (channel 0 >1).
Priority level of the channel
requested for transfer is kept
lowest.
2. SRAM access function : 1 bank
Supports 16-bit devices
Supports asynchronous SRAM
Configurable access timing.
3. Maximum number 65,536 per DMA operation.
of transfers:
3. DRAM access function : 1 bank
4. Data transfer size: Byte (8 bits), Half-word (16 bits), Word (32 bits)
Supports 16-bit devices
Supports EDO-DRAM/SDRAM: Simultaneous connections to EDO-DRAM
and SDRAM cannot be made.
5. Bus request
system:
Cycle steal
mode:
Bus request signal is asserted for
each DMA transfer cycle.
Configurable access timing.
Burst mode:
Bus request signal is asserted until
all transfers of transfer cycles are
complete.
4. External I/O access function: 2 banks
Supports 8-bit/16-bit access: Independent configuration for each bank.
Each bank has two chip selects: XIOCS_N[3:0].
Supports external wait input: XWAIT
6. DMA transfer
request:
Software
request:
By setting the software transfer
request bit inside the DMAC, the
CPU starts DMA transfer.
Access timing configurable for bank independently.
External
request:
DMA transfer is started by exter-
nal request allocated to each
channel.
GPIO
42-bit parallel port (four 8-bit ports and one 10-bit port).
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]
Combination port
Combination port
Combination port
Combination port
Combination port
UART
7. Interrupt request: Interrupt request is generated in CPU after the end
of DMA transfer for the set number of transfer
DMAC, SIO (µPLAT-7B)
PWM, XA[23:19], XWR
DRAM control signals etc.
SSIO, I2C, External interrupt signal
cycles, or after the occurrence of an error.
Interrupt request signal is output separately for
each channel.
Interrupt request signal output can be masked for
each channel.
1. Input/output selectable at bit level.
2. Each bit can be used as an interrupt source.
3. Interrupt mask and interrupt priority can be set for all bits.
4. The ports are configured as input, immediately after reset.
5. Primary/secondary function of each port can be set independently.
4 • Oki Semiconductor
April 2004, Rev 2.0
OKI [ OKI ELECTRONIC COMPONETS ]
