ML674001/ML67Q4002/ML67Q4003
Pin Descriptions (Continued)
Primary/
Pin Name
I/O
Description
Secondary
Logic
I2C
SDA
SCL
I/O
O
I2C Data; open-drain pin needs an external pullup resistor
I2C Clock; open-drain pin needs an external pullup resistor
Secondary
Secondary
—
—
Synchronous SIO
SCLK
SDI
I/O
I
Serial clock
Secondary
Secondary
Secondary
—
—
—
Serial receive data
Serial transmit data
SDO
O
Pulse Width Modulator (PWM) signals
PWMOUT[0]
O
O
PWM output of Ch 0
PWM output of Ch 1
Secondary
Secondary
Positive
Positive
PWMOUT[1]
Analog-to-digital converter
AIN[0]
I
I
I
I
I
Ch 0 analog input
—
—
—
—
—
—
—
—
—
—
AIN[1]
Ch 1 analog input
AIN[2]
Ch 2 analog input
AIN[3]
Ch 3 analog input
VREF
Analog-to-digital converter convert reference voltage
Interrupt signals
EXINT[3:0]
EFIQ_N
I
I
Interrupt input signals
Secondary
Secondary
Positive / Negative
Negative
Negative-edge-triggered interrupt input signal.
Interrupt controller connects this signal to CPU FIQ input.
MODE configuration
DRAME_N
TEST
I
I
I
I
DRAM enable mode
—
Negative
Positive
Positive
—
Test mode
FWR
Flash ROM write enable signal
JTAG select signal. L = On-board debug, H = Boundary scan.
—
—
JSEL
Power supplies
AVDD
Analog-to-digital converter power supply, 3.3 V
Analog-to-digital converter ground
Core power supply, 2.5 V
—
—
—
—
—
—
—
—
—
—
AGND
VDD_CORE
VDD_IO
I/O power supply, 3.3 V
GND
GND for core and I/O
14 • Oki Semiconductor
April 2004, Rev 2.0
OKI [ OKI ELECTRONIC COMPONETS ]
