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ML67Q4003LA 参数 Datasheet PDF下载

ML67Q4003LA图片预览
型号: ML67Q4003LA
PDF下载: 下载PDF文件 查看货源
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分类和应用:
文件页数/大小: 19 页 / 645 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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ML674001/ML67Q4002/ML67Q4003  
Pin Descriptions (Continued)  
Primary/  
Pin Name  
I/O  
O
Description  
Secondary  
Logic  
Negative  
Negative  
Negative  
Negative  
Negative  
XOE_N  
XWE_N  
Output enable/ Read enable  
Write enable  
O
XBS_N[1:0]  
XBWE_N[0]  
XBWE_N[1]  
XWR  
O
Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB  
LSB Write enable  
O
O
MSB Write enable  
O
Data transfer direction for external bus, used when connecting to Motorola I/O devices.This  
represent the secondary function of pin PIOC[7].  
Secondary  
L = read, H = write. Available for I/O bank 0/1.  
XWAIT  
I
External I/O bank 0/1, 2/3 WAIT signal.  
Secondary  
Positive  
This input permits access to devices slower than register settings.  
External bus control signals (EDO-DRAM/SDRAM)  
XRAS_N  
XCAS_N  
XSDCLK  
XSDCKE  
XSDCS_N  
O
O
O
O
O
O
Row address strobe. Used for both EDO DRAM and SDRAM  
Column address strobe signal (SDRAM)  
SDRAM clock (same frequency as internal system clock)  
Clock enable (SDRAM)  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Negative  
Negative  
Chip select (SDRAM)  
Negative  
XDQM[1]/  
XCAS_N[1]  
Connected to SDRAM: DQM (MSB)  
Connected to EDO-DRAM: column address strobe signal (MSB)  
Positive/  
Negative  
XDQM[0]/  
XCAS_N[0]  
O
Connected to SDRAM: DQM (LSB)  
Connected to EDO-DRAM: column address strobe signal (LSB)  
Secondary  
Positive/  
Negative  
DMA control signals  
DREQ[0]  
I
Ch 0 DMA request signal, used when DMA controller configured for DREQ type  
Ch 0 DREQ signal clear request.The DMA device responds to this output by negating DREQ.  
Indicates to Ch 0 DMA device that last transfer has started.  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Positive  
Positive  
Positive  
Positive  
Positive  
Positive  
DREQCLR[0]  
TCOUT[0]  
DREQ[1]  
O
O
I
Ch 1 DMA request signal, used when DMA controller configured for DREQ type.  
Ch 1 DREQ signal clear request.The DMA device responds to this output by negating DREQ.  
Indicates to Ch 1 DMA device that last transfer has started.  
DREQCLR[1]  
TCOUT[1]  
UART  
O
O
SIN  
I
O
I
UART receive signal.  
UART transmit signal.  
Clear To Send.  
Secondary  
Secondary  
Secondary  
Positive  
Positive  
Negative  
SOUT  
CTS  
Indicates that modem or data set is ready to transfer data. Bit 4 in the modem status reg-  
ister reflects this input.  
DSR  
I
Data Set Ready.  
Secondary  
Negative  
Indicates that modem or data set is ready to establish a communications link with UART.  
Bit 5 in the modem status register reflects this input.  
DCD  
DTR  
RTS  
RI  
I
Data Carrier Detect.  
Secondary  
Secondary  
Secondary  
Secondary  
Negative  
Negative  
Negative  
Negative  
Indicates that modem or data set has detected data carrier signal.Bit 7 in the modem sta-  
tus register reflects this input.  
O
O
O
Data Terminal Ready.  
Indicates that UART is ready to establish a communications link with the modem or data  
set. Bit 0 in the modem control register controls this output.  
Request To Send.  
indicates that UART is ready to transfer data to modem or data set. Bit 1 in the modem  
control register controls this output.  
Ring Indicator. Indicates that the modem or data set has received a telephone ring indica-  
tor. Bit 6 in the modem status register reflects this input.  
SIO  
STXD  
SRXD  
O
I
SIO transmit signal  
SIO receive signal  
Secondary  
Secondary  
Positive  
Positive  
April 2004, Rev 2.0  
Oki Semiconductor • 13  
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