¡ Semiconductor
ML54053
3.2 NAND Flash Memory Interface
Signal Name Type Pin Count
Description
maio [7:0]
macle
B
O
8
1
Port A I/O bus
Port A command latch enable signal (signal to control latching of an
operation command into a device)
maale
O
1
Port A address latch enable signal (signal to control latching of an address
or input data into a device)
maren
O
O
I
1
1
1
8
1
Port A read enable signal
mawen
marbn
Port A write enable signal (signal to latch data into a device)
Port A ready/busy signal (signal to check internal status of device)
Port B I/O bus
mbio [7:0]
mbcle
B
O
Port B command latch enable signal (signal to control latching of an
operation command into a device)
mbale
O
1
Port B address latch enable signal (signal to control latching of an address
or input data into a device)
mbren
O
O
I
1
Port B read enable signal
mbwen
mbrbn
1
Port B write enable signal (signal to latch data into a device)
Port B ready/busy signal (signal to check internal status of device)
Chip enable signals
1
mcen [3:0]
mwpn
O
O
4
1
Write protect signal (signal to forcibly prohibit write and erase operations)
Total 31 pins
3.3 Extended Bus Interface
The extended bus interface is a signal line for the ML54053’s internal microcontroller. The
extended bus interface is used for purposes such as debugging.
Signal Name Type Pin Count
Description
xah [15:8]
xad [7:0]
xrd
B
B
B
B
B
I
8
Address bus for extended bus
8
Address/data bus for extended bus
Read signal for extended bus
1
xwr
1
Write signal for extended bus
xale
1
Address latch enable signal for extended bus
Program store enable signal for extended bus
Interrupt signal for extended bus
Reset signal for extended bus
xpsen
xint
1
O
O
O
1
xrst
1
xclk
1
Clock signal for extended bus
Total 23 pins
*
In an external ROM connection mode, xah, xad, xrd, xwr, and xale are used to connect to
external ROM.
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