¡ Semiconductor
ML54053
3. PIN SPECIFICATIONS
Refer to Section 11, “Application Example” for specific connection examples.
3.1 Host Interface
Signal Name Type
ha [10:0]
hd [15:0]
hcen [2:1]
I
B
I
Pin Count
11
16
2
Description
Address bus (A10 is MSB, A0 is LSB)
Data bus (D15 is MSB, D0 is LSB)
Card enable signal (hcen1 controls even addresses and hcen2 controls odd
addresses. The combination of ha0, hcen1 and hcen2 allows even/odd
addresses to be accessed by hd[7:0].)
hiordn
hiowrn
hoen
hwen
hregn
hirqn
hstschgn
hinpackn
hiois16n
hwaitn
hspkr
hrst
hcseln
I
I
I
I
I
O
O
O
O
O
B
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
Total 42 pins
I/O read signal (control signal to read data from ATA registers)
I/O write signal (control signal to write data to ATA registers)
Output enable signal
Write enable signal
Register select & I/O Enable signal
Interrupt request signal (when the card is configured as an I/O card)
Card status change signal (signal to change the status of the configuration
status register)
Input port acknowledge signal (acknowledge signal during I/O read)
16-bit address enable signal (when the card is configured as an I/O card,
this signal indicates that 16-bit addresses are enabled)
Wait signal
Audio digital waveform signal
Reset signal
Cable select signal (used only in True IDE Mode, GND: Master, X: Slave)
I: Input, O: Output, B: Bidirectional
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