MK31VT872A-8YC 98.06.26
SERIAL PRESENCE DETECT
Byte
SPD
Remark
Notes
No.
Hex Value
Defines the number of bytes written into
SPD memory
0
80
128 byte
1
2
08
04
0C
09
01
48
00
01
80
60
02
80
08
08
01
8F
04
06
01
01
00
0E
C0
A0
00
00
1E
10
14
30
10
20
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
256 byte
SDRAM
12 rows
9 columns
1 bank
3
4
Number of columns
5
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
6
72 bits
0
7
8
LVTTL
CL=3 tCC=8ns
CL=3 tAC3=6ns
ECC
Normal/ Self/
x8
9
Cycle time (CL=3)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
Command and address signal input setup time
Command and address signal input hold time
x8
tCCD: 1 CLK
1,2,4,8,F
4 banks
2,3
0
0
CL=2 tCC2=12ns
CL=2 tAC2=10ns
Not support
Not support
tRP=30ns
tRRD=16ns
tRCD=20ns
tRAS=48ns
64MB
2ns
1ns
2ns
1ns
10
20
10
00-00
Data signal input setup time
Data signal input hold time
R.F.U
1.2
12
SPD data revision code
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
5B
41,45,20,20,20,20,20,20
01/06
73-90 4D,4B,33,31,56,54,38,37,32, Manufacturer’s part number
41,2D,38,59,43,20,20,20,202
MK31VT872A-8YC
91,92
93-125
126
20,20
00-00
64
A5
FF-FF
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
100MHz
(CLK0-2,CL=3)
127
128-255
OKI [ OKI ELECTRONIC COMPONETS ]
