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MK31VT872A 参数 Datasheet PDF下载

MK31VT872A图片预览
型号: MK31VT872A
PDF下载: 下载PDF文件 查看货源
内容描述: 8388608字X 72位同步动态RAM模块( 1BANK ) [8,388,608 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK)]
分类和应用:
文件页数/大小: 11 页 / 106 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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MK31VT872A-8YC 98.06.26
Ñ
Ò
AC CHARACTERISTIC
Parameter
Clock Cycle Time
Access Time from Clock
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Setup Time
Input Hold Time
Output Low Impedance Time from Clock
Output High Impedance Time from Clock
Output Hold from Clock
/RAS Cycle Time
/RAS Precharge Time
/RAS Active Time
/RAS to /CAS Delay Time
Write Recovery Time
/RAS to /RAS Bank Active Delay Time
Refresh Time
Power-down Exit Set-up Time
Input Level Transition Time
/CAS to /CAS Delay Time (Min)
Clock Disable Time from CKE
Data Output High Impedance Time from
Data Input Mask Time from DQMB
Data Input Time from Write Command
Data Output High Inpedance
CL=3
Time from Precharge Command
CL=2
Active Command Input Time from MODE
Write Command Input Time from Output
NOTES:
1)
2)
3)
4)
5)
CL=3
CL=2
CL=3
CL=2
tCH
tCL
tSI
tHI
tOLZ
tOHZ
tOH
tRC
tRP
tRAS
tRCD
tWR
tRRD
tREF
tPDE
tT
ICCD
ICKE
IDOZ
IDOD
IDWD
IROH
IMRD
tOWD
Symbol
tCC
tAC
(Vcc=3.3V
±
0.3V,Ta = 0 to 70 °C)
NOTE 1,2
Module Spec.
Unit Note
Min.
Max.
8
12
-
-
3
3
2
1
3
-
3
80
30
48
20
8
16
-
tSI+1CLK
-
1
1
2
0
0
3
2
2
2
-
-
6
10
-
-
-
-
-
8
-
-
-
100,000
-
-
-
64
-
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
.
3,4
3,4
3
AC measurements assume tT=1ns.
The reference level for timing of input signals is 1.4V.
This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF
(R Load is 50ohm).
An access time is measured at 1.4V.
If tT is longer than 1ns, the reference level for timing of input signals are V
IH
and V
IL.
®«±ó
50Ω
ÌÒÑÍÒÑ
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OUTPUT LOAD