MSM6242B
¡ Semiconductor
FUNCTIONAL DESCRIPTION OF REGISTERS
S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1, Y10, W
a) These are abbreviations for SECOND1, SECOND10, MINUTE1, MINUTE10, HOUR1,
HOUR10, DAY1, DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These
values are in BCD notation.
b) All registers are logically positive. For example, (S8, S4, S2, S1) = 1001 which means 9
seconds.
c) Ifdataiswrittenwhichisoutoftheclockregisterdatalimits, itcanresultinerroneousclock
data being read back.
d) PM/AM, h20, h10
In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the setting of 12-hour
mode h20 is to be set. Otherwise it causes a discrepancy. In reading out the PM/AM bit in
the24-hourmode,itiscontinuouslyreadoutas0. Inreadingouth bitinthe12-hourmode,
0 is written into this bit first, then it is continuously read out as 02u0 nless 1 is being written
into this bit.
e) Registers Y1, Y10, and Leap Year. The MSM6242B is designed exclusively for the Christian
Eraandiscapableofidentifyingaleapyearautomatically. Theresultofthesettingofanon-
existant day of the month is shown in the following example: If the date February 29 or
November 31, 1985, was written, it would be changed automatically to March 1, or
December 1, 1985 at the exact time at which a carry pulse occurs for the day's digit.
f) The Register W data limits are 0 – 6 (Tabel 1 shows a possible data definition).
TABLE 1
Day of Week
Sunday
w4
0
w2
0
w1
0
Monday
0
0
1
Tuesday
Wednesday
Thursday
Friday
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
Saturday
Using HOLD Bit
Not Using HOLD Bit
Read Register
1 ~ W
←
HOLD Bit
1
First
S
Read BUSY Bit
Data of
S1 ~ W
Register
←
DATA
*
NO
HOLD Bit
Busy Bit= O?
YES
Read Register
S1 ~ W
Second
←
0
DATA1 = DATA2
Write data into
or Read data from
registers S1 ~ W
*
In the inside of LSI, the CLEAR of BUSY bit is performed when
HOLD bit = 0, but, if the period of HOLD bit =0 is extermely
narrow as compared with the period of HOLD bit = 1, there is
some case that the CLEAR of BUSY bit delays so that the
BUSY bit can be cleared by sampling HOLD bit = 0 at approximate
16KHz. It is recommended to allow an idling time of 62ms or more.
Idling Time
NO
DATA1 = DATA2
YES
←
HOLD Bit
0
Figure 10. Reading and Writing of Registers S1 ~ W
32
OKI [ OKI ELECTRONIC COMPONETS ]
