M541 参数 Datasheet PDF下载

¡ Semiconductor

MSM5412222

OPERATION

Write Operation

The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is

accomplished by cycling SWCK, and holding WE high after the write address pointer reset

operation or RSTW.

Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e.

SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time

is stored in the serial data registers attached to the DRAM array, an RSTW operation is required

after the last SWCK cycle.

Note that every write timing of MSM5412222 is delayed by one clock compared with read timings

for easy cascading without any interface delay devices.

Write Reset : RSTW

The first positive transition of SWCK after RSTW becomes high resets the write address counters

to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write

reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states

of WE and IE are ignored in the write reset cycle.

Before RSTW may be brought high again for a further reset operation, it must be low for at least

two SWCK cycles.

Data Inputs : D

IN

0 - 11

Write Clock : SWCK

The SWCK latches the input data on chip when WE is high, and also increments the internal write

address pointer. Data-in setup time t

DS

, and hold time t

DH

are referenced to the rising edge of

SWCK.

Write Enable : WE

WE is used for data write enable/disable control. WE high level enables the input, and WE low

level disables the input and holds the internal write address pointer. There are no WE disable

time (low) and WE enable time (high) restrictions, because the MSM5412222 is in fully static

operation as long as the power is on. Note that WE setup and hold times are referenced to the

rising edge of SWCK.

Input Enable : IE

IE is used to enable/disable writing into memory. IE high level enables writing. The internal

write address pointer is always incremented by cycling SWCK regardless of the IE level. Note

that IE setup and hold times are referenced to the rising edge of SWCK.

5/15