¡ Semiconductor
MSM5412222
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset
operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
NotethateverywritetimingofMSM5412222isdelayedbyoneclockcomparedwithreadtimings
for easy cascading without any interface delay devices.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters
tozero. RSTWsetupandholdtimesarereferencedtotherisingedgeofSWCK. Becausethewrite
resetfunctionissolelycontrolledbytheSWCKrisingedgeafterthehighlevelofRSTW,thestates
of WE and IE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Data Inputs : D 0 - 11
IN
Write Clock : SWCK
TheSWCKlatchestheinputdataonchipwhenWEishigh, andalsoincrementstheinternalwrite
address pointer. Data-in setup time t , and hold time t
are referenced to the rising edge of
DS
DH
SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low
level disables the input and holds the internal write address pointer. There are no WE disable
time (low) and WE enable time (high) restrictions, because the MSM5412222 is in fully static
operation as long as the power is on. Note that WE setup and hold times are referenced to the
rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal
write address pointer is always incremented by cycling SWCK regardless of the IE level. Note
that IE setup and hold times are referenced to the rising edge of SWCK.
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