11AA02E48/11AA02E64
There are two variables which can cause the
11AA02EXX to lose synchronization. The first is
frequency drift, defined as a change in the bit
period, TE. The second is edge jitter, which is a single
occurrence change in the position of an edge within a
bit period, while the bit period itself remains constant.
3.6
Device Standby
The 11AA02EXX features a low-power Standby mode
during which the device is waiting to begin a new
command. A high-to-low transition on SCIO will exit
low-power mode and prepare the device for receiving
the start header.
3.8.1
FREQUENCY DRIFT
Standby mode will be entered upon the following
conditions:
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some
tolerance for such frequency drift. The tolerance range
is specified by two parameters, FDRIFT and FDEV.
FDRIFT specifies the maximum tolerable change in bus
frequency per byte. FDEV specifies the overall limit in
frequency deviation within an operation (i.e., from the
end of the start header until communication is
terminated for that operation). The start header at the
beginning of the next operation will reset the
re-synchronization circuitry and allow for another FDEV
amount of frequency drift.
• A NoMAK followed by a SAK
(i.e., valid termination of a command)
• Reception of a standby pulse
Note:
In the case of the WRITE, WRSR, SETAL,
or ERAL commands, the write cycle is
initiated upon receipt of the NoMAK,
assuming all other write requirements
have been met.
3.7
Device Idle
The 11AA02EXX features an Idle mode during which
all serial data is ignored until a standby pulse occurs.
Idle mode will be entered upon the following
conditions:
3.8.2
EDGE JITTER
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization
circuitry is designed to provide some tolerance for edge
jitter.
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle
The 11AA02EXX adjusts its phase every MAK bit, so
TIJIT specifies the maximum allowable peak-to-peak
jitter relative to the previous MAK bit. Since the position
of the previous MAK bit would be difficult to measure by
the master, the minimum and maximum jitter values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
• Missed edge transition
• Reception of a MAK following a WREN, WRDI,
SETAL, or ERAL command byte
• Reception of a MAK following the data byte of a
WRSR command
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, an edge transition will be missed, thus causing
the device to enter Idle mode.
The difference between the minimum and maximum
values, as a percentage of the bit period, should be
calculated and then compared against TIJIT to
determine jitter compliance.
Note:
Because
the
11AA02EXX
only
3.8
Synchronization
re-synchronizes during the MAK bit, the
overall ability to remain synchronized
depends on a combination of frequency
drift and edge jitter (i.e., if the MAK bit
edge is experiencing the maximum
allowable edge jitter, then there is no room
for frequency drift). Conversely, if the
frequency has drifted to the maximum
amount tolerable within a byte, then no
edge jitter can be present.
At the beginning of every command, the 11AA02EXX
utilizes the start header to determine the master’s bus
clock period. This period is then used as a reference for
all subsequent communication within that command.
The 11AA02EXX features re-synchronization circuitry
which will monitor the position of the middle data edge
during each MAK bit and subsequently adjust the
internal time reference in order to remain synchronized
with the master.
DS20002122D-page 8
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