5NP4G
Contents
7.3.3.2 Execute Indirect Opcode .............................................................................................. 216
7.3.3.3 Execute Direct Conditional Opcode .............................................................................. 217
7.3.3.4 Execute Indirect Conditional Opcode ........................................................................... 217
7.3.3.5 Wait Opcode ................................................................................................................. 218
7.3.3.6 Wait and Branch Opcode ............................................................................................. 218
7.3.4 ALU Opcodes ....................................................................................................................... 219
7.3.4.1 Arithmetic Immediate Opcode ...................................................................................... 219
7.3.4.2 Logical Immediate Opcode ........................................................................................... 222
7.3.4.3 Compare Immediate Opcode ....................................................................................... 223
7.3.4.4 Load Immediate Opcode .............................................................................................. 224
7.3.4.5 Arithmetic Register Opcode .......................................................................................... 227
7.3.4.6 Count Leading Zeros Opcode ...................................................................................... 229
7.4 DPPU Coprocessors ..................................................................................................................... 230
7.4.1 Tree Search Engine Coprocessor ........................................................................................ 231
7.4.2 Data Store Coprocessor ...................................................................................................... 231
7.4.2.1 Data Store Coprocessor Address Map ......................................................................... 232
7.4.2.2 Data Store Coprocessor Commands ............................................................................ 239
7.4.3 Control Access Bus (CAB) Coprocessor ............................................................................. 248
7.4.3.1 CAB Coprocessor Address Map ................................................................................... 248
7.4.3.2 CAB Access to 5NP4G Structures ............................................................................... 249
7.4.3.3 CAB Coprocessor Commands ..................................................................................... 250
7.4.4 Enqueue Coprocessor ......................................................................................................... 251
7.4.4.1 Enqueue Coprocessor Address Map ............................................................................ 252
7.4.4.2 Enqueue Coprocessor Commands .............................................................................. 265
7.4.5 Checksum Coprocessor ....................................................................................................... 270
7.4.5.1 Checksum Coprocessor Address Map ......................................................................... 270
7.4.5.2 Checksum Coprocessor Commands ............................................................................ 271
7.4.6 String Copy Coprocessor ..................................................................................................... 275
7.4.6.1 String Copy Coprocessor Address Map ....................................................................... 275
7.4.6.2 String Copy Coprocessor Commands .......................................................................... 275
7.4.7 Policy Coprocessor .............................................................................................................. 276
7.4.7.1 Policy Coprocessor Address Map ................................................................................ 276
7.4.7.2 Policy Coprocessor Commands ................................................................................... 276
7.4.8 Counter Coprocessor ........................................................................................................... 277
7.4.8.1 Counter Coprocessor Address Map ............................................................................. 277
7.4.8.2 Counter Coprocessor Commands ................................................................................ 278
7.4.9 Coprocessor Response Bus ................................................................................................ 281
7.4.9.1 Coprocessor Response Bus Address Map ................................................................... 281
7.4.9.2 Coprocessor Response Bus Commands ..................................................................... 281
7.4.9.3 14-bit Coprocessor Response Bus ............................................................................... 282
7.4.10 Semaphore Coprocessor ................................................................................................... 282
7.4.10.1 Semaphore Coprocessor Commands ........................................................................ 282
7.4.10.2 Error Conditions .......................................................................................................... 284
7.4.10.3 Software Use Models ................................................................................................. 285
7.5 Interrupts and Timers .................................................................................................................... 286
7.5.1 Interrupts .............................................................................................................................. 286
7.5.1.1 Interrupt Vector Registers ............................................................................................. 286
7.5.1.2 Interrupt Mask Registers .............................................................................................. 286
7.5.1.3 Interrupt Target Registers ............................................................................................. 286
7.5.1.4 Software Interrupt Registers ......................................................................................... 286
Contents
Page 6 of 607
5NP4G Network Processor, Data Sheet, DS-0125-02
January 2006
EXAR [ EXAR CORPORATION ]
