5NP4G
Contents
6. Egress Enqueuer / Dequeuer / Scheduler ............................................................ 167
6.1 Functional Blocks .......................................................................................................................... 168
6.2 Operation ...................................................................................................................................... 171
6.3 Egress Flow Control ...................................................................................................................... 175
6.3.1 Flow Control Hardware Facilities ......................................................................................... 175
6.3.2 Remote Egress Status Bus ................................................................................................. 176
6.3.2.1 Bus Sequence and Timing ........................................................................................... 176
6.3.2.2 Configuration ................................................................................................................ 178
6.3.3 Hardware Function .............................................................................................................. 180
6.3.3.1 Exponentially Weighted Moving Average ..................................................................... 181
6.3.3.2 Flow Control Hardware Actions .................................................................................... 181
6.4 The Egress Scheduler ................................................................................................................... 182
6.4.1 Egress Scheduler Components ........................................................................................... 184
6.4.1.1 Scheduling Calendars .................................................................................................. 184
6.4.1.2 Flow Queues ................................................................................................................ 185
6.4.1.3 Target Port Queues ...................................................................................................... 187
6.4.2 Configuring Flow Queues .................................................................................................... 188
6.4.2.1 Additional Configuration Notes ..................................................................................... 188
6.4.3 Scheduler Accuracy and Capacities .................................................................................... 188
7. Embedded Processor Complex ............................................................................. 191
7.1 Overview ....................................................................................................................................... 191
7.1.1 Thread Types ...................................................................................................................... 195
7.2 Dyadic Protocol Processor Unit (DPPU) ....................................................................................... 196
7.2.1 Core Language Processor (CLP) ........................................................................................ 198
7.2.1.1 Core Language Processor Address Map ..................................................................... 200
7.2.2 CLP Opcode Formats .......................................................................................................... 201
7.2.3 DPPU Coprocessors ........................................................................................................... 201
7.2.4 Shared Memory Pool ........................................................................................................... 201
7.3 CLP Opcode Formats ................................................................................................................... 203
7.3.1 Control Opcodes .................................................................................................................. 203
7.3.1.1 Nop Opcode ................................................................................................................. 204
7.3.1.2 Exit Opcode .................................................................................................................. 204
7.3.1.3 Test and Branch Opcode ............................................................................................. 204
7.3.1.4 Branch and Link Opcode .............................................................................................. 205
7.3.1.5 Return Opcode ............................................................................................................. 205
7.3.1.6 Branch Register Opcode .............................................................................................. 206
7.3.1.7 Branch PC Relative Opcode ........................................................................................ 206
7.3.1.8 Branch Reg+Off Opcode .............................................................................................. 206
7.3.2 Data Movement Opcodes .................................................................................................... 207
7.3.2.1 Memory Indirect Opcode .............................................................................................. 211
7.3.2.2 Memory Address Indirect Opcode ................................................................................ 212
7.3.2.3 Memory Direct Opcode ................................................................................................ 213
7.3.2.4 Scalar Access Opcode ................................................................................................. 213
7.3.2.5 Scalar Immediate Opcode ............................................................................................ 214
7.3.2.6 Transfer Quadword Opcode ......................................................................................... 214
7.3.2.7 Zero Array Opcode ....................................................................................................... 214
7.3.3 Coprocessor Execution Opcodes ........................................................................................ 215
7.3.3.1 Execute Direct Opcode ................................................................................................ 216
5NP4G Network Processor, Data Sheet, DS-0125-02
January 2006
Contents
Page 5 of 607
EXAR [ EXAR CORPORATION ]
