.
5NP4G
Contents
Contents
List of Tables ................................................................................................................. 13
List of Figures .............................................................................................................. 21
About This Book .......................................................................................................... 25
Note: Who Should Read This Manual ................................................................................................... 25
Note: Related Publications .................................................................................................................... 25
Note: Conventions Used in This Manual ............................................................................................... 25
1. General Information .................................................................................................. 27
1.1 Features .......................................................................................................................................... 27
1.2 Ordering Information ....................................................................................................................... 28
1.3 Overview ......................................................................................................................................... 28
1.4 5NP4G-Based Systems .................................................................................................................. 28
1.5 Structure .......................................................................................................................................... 30
1.5.1 EPC Structure ........................................................................................................................ 31
1.5.1.1 Coprocessors ................................................................................................................. 32
1.5.1.2 Enhanced Threads ......................................................................................................... 32
1.5.1.3 Hardware Accelerators ................................................................................................... 33
1.5.2 5NP4G Memory ..................................................................................................................... 33
1.6 Data Flow ........................................................................................................................................ 34
1.6.1 Basic Data Flow ..................................................................................................................... 34
1.6.2 Data Flow in the EPC ............................................................................................................ 35
2. Physical Description ................................................................................................. 39
2.1 Pin Information ................................................................................................................................ 40
2.1.1 Packet Routing Switch Interface Pins .................................................................................... 42
2.1.2 Flow Control Interface Pins ................................................................................................... 44
2.1.3 ZBT Interface Pins ................................................................................................................. 45
2.1.4 DDR DRAM Interface Pins .................................................................................................... 48
2.1.4.1 D3, D2, D1, and D0 Interface Pins ................................................................................. 54
2.1.4.2 D4_0 and D4_1 Interface Pins ....................................................................................... 57
2.1.4.3 D6_x Interface Pins ........................................................................................................ 58
2.1.4.4 DS1 and DS0 Interface Pins .......................................................................................... 59
2.1.5 PMM Interface Pins ............................................................................................................... 60
2.1.5.1 TBI Bus Pins ................................................................................................................... 64
2.1.5.2 GMII Bus Pins ................................................................................................................ 67
2.1.5.3 SMII Bus Pins ................................................................................................................. 70
2.1.5.4 POS Bus Pins ................................................................................................................. 72
2.1.6 PCI Pins ................................................................................................................................. 77
2.1.7 Management Bus Interface Pins ........................................................................................... 81
2.1.8 Miscellaneous Pins ................................................................................................................ 83
2.1.9 PLL Filter Circuit .................................................................................................................... 86
2.1.10 Thermal I/O Usage .............................................................................................................. 87
2.1.10.1 Temperature Calculation .............................................................................................. 87
2.1.10.2 Measurement Calibration ............................................................................................. 88
5NP4G Network Processor, Data Sheet, DS-0125-02
January 2006
Contents
Page 3 of 607
EXAR [ EXAR CORPORATION ]
