EtronTech
EM6A9160
8Mx16 DDR SDRAM
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and
WE#. The state of A0, A2 ~ A5, A7 ~ A11and BS1 is written in the mode register in the same cycle as CS#,
RAS#, CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high
prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak
or matched impedance. Two clock cycles are required to complete the write operation in the extended mode
register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BS0
is used for EMRS. Refer to the table for specific codes.
Extended Mode Resistor Bitmap
BS1
0
BS0
1
A11
A10
A9
A8
A7
A6
DS1
A5
A4
A3
A2
A1
DS0
A0
DLL
RFU must be set to “0”
RFU must be set to “0”
BS0 Mode
A6 A1
Drive Strength
Full
Strength
100%
60%
Comment
A0
0
1
DLL
0
0
1
1
0
1
0
0
1
MRS
EMRS
Enable
Disable
SSTL-2 weak
RFU
RFU Reserved For Future
1 Matched impedance 30%
Output driver matches impedance
9
Rev. 1.4
May 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
