EtronTech
EM6A9160
8Mx16 DDR SDRAM
CAS Latency Field (A6~A4)
•
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS Latency depends on the frequency of
CK. The minimum whole value satisfying the following formula must be programmed into this
field. tCAC(min) ≤ CAS Latency X tCK
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
Reserved
3 clocks
0
0
1
0
1
0
0
1
1
1
0
0
4 clocks
1
0
1
Reserved
Reserved
Reserved
1
1
0
1
1
1
Test Mode field (A8~A7)
•
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8
0
A7
0
Test Mode
Normal mode
DLL Reset
1
0
X
1
Test mode
( BS0, BS1)
•
BS1
RFU
RFU
BS0
0
An ~ A0
MRS Cycle
1
Extended Functions (EMRS)
8
Rev. 1.4
May 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
