ES1988 PRODUCT BRIEF
Table 1 ES1988 Pin Descriptions (Continued)
Name
Pin Number
I/O
Description
PME#
O
PME# output to wake up the system. PME is enabled by setting the PME_EN bit (PCI C5h [0]
= 1).
SPDIFO
PCGNT#
VOLDN#
O
I
S/PDIF Output. Enable SPDIFO by setting PCI 53h [0] = 1. Select SPDIFO from pin 54 by
setting PCI 58h [1] = 0. Either pin 2 or pin 54 may be used for SPDIFO.
PC/PCI grant input. Enable PC/PCI by setting PCI 50h [10:8] = 010. Select PCGNT# from pin
54 by setting Allegro_Base+58h [6] = 1. Either pin 54 or pin 63 may be used for PCGNT#.
54
I
Hardware volume control (volume down). Used in combination with pin 53 (VOLUP#).
Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 53:54 is selected for
hardware volume control by setting PCI 52h [5] = 0. Pins 44:45 may also be used for
hardware volume control.
VAUX
SDI2
I
I
3.3 volt VAUX voltage supply input. If VAUX is not supported, then VAUX (pin 55) should be
connected to VCC and VAUXD (pin 62) should be pulled down.
55
56
External AC-link serial data input. Select secondary Codec by enabling Allegro_Base+38h [5]
= 1.
GPIO8
I/O
I
General-purpose input/output.
49.152-MHz crystal input.
49.152-MHz crystal output.
OSCI
57
58
OSCO
O
O
SRESET2#
Reset output for AC-Link interface. Select secondary Codec by enabling Allegro_Base+38h
[5] = 1.
59
60
61
GPIO3
SDFS2
I/O
O
General-purpose input/output.
Serial data frame sync output for AC-Link interface. Select secondary Codec by enabling
Allegro_Base+38h [5] = 1.
GPIO9
(note)
I/O
General purpose input/output.
If a pull-down resistor is used on this pin, the ES1988 is configured as a multifunction device
(audio-modem). Otherwise, the ES1988 is configured as a single function audio-only device.
SCLK2
O
Serial clock for AC-link interface. Select secondary Codec by enabling Allegro_Base+38h [5]
= 1.
GPIO10
SDO2
I/O
O
General-purpose input/output.
External AC-link serial data output. Select secondary Codec by enabling Allegro_Base+38h
[5] = 1.
GPIO11
VAUXD
I/O
I
General-purpose input/output.
62
V
AUX detect. During the reset period, the VAUXD pin is driven high to indicate ACPI support in
the D3cold state, and is driven low to indicate ACPI is not supported in the D3cold state. If VAUX
is not supported, then VAUX (pin 55) should be connected to VCC and VAUXD (pin 62) should
be pulled down.
PCGNT#
GT0#
I
PC/PCI grant input. Enable PC/PCI by setting PCI 50h [10:8] = 010. Select PCGNT# from pin
63 by setting Allegro_Base+58h [6] = 0. Either pin 54 or pin 63 may be used for PCGNT#.
O
Grant to PCI master. GTO# is enabled by setting PCIx2 arbiter bits PCI 58h [0] = 1 and PCI
58h [11] = 1. Select GT0#/GSO from pin 63 by enabling PCI 58h [10] = 1. Pin 51 may also be
used as GT0#/GSO.
63
GS0
O
Grant select 0 output to control external quick switch to grant PCI master phase. GSO is
enabled by setting PCIx2 arbiter bit PCI 58h [0] = 1 and PCI 58h [11] = 0. Select GS0/GT0#
from pin 63 by enabling PCI 58h [10] = 1. Pin 51 may also be used as GT0#/GSO.
GPIO12
I/O
General-purpose input/output.
ESS Technology, Inc.
SAM0368-051302
5
ESS [ ESS Technology,Inc ]
