ES1988 PRODUCT BRIEF
PIN DESCRIPTION
Table 1 lists the ES1988 pin descriptions.
Table 1 ES1988 Pin Descriptions
Name
Pin Number
I/O
Description
C/BE[3:0]#
I/O
PCI command/byte enable. During address phase of a transaction, these pins define the bus
command. During data phase, these pins define the byte enable.
1, 13, 20, 30
IDSEL
R0#
I
I
ID Select. When pin 2 is configured as a multifunction pin (see pin 2 note), IDSEL is selected
internally to AD24.
PCI bus request 0 input from external PCI master device. RO# is enabled by setting the
PCIx2 arbiter bit PCI 58h [0] = 1. Select RO# from pin 2 by setting PCI 58h [10] = 1, and pin 2
must be configured as a multifunction pin (see pin 2 note). Either pin 2 or pin 52 may be used
for R0#.
SPDIFO
O
O
S/PDIF Output. Enable SPDIFO by setting PCI 53h [0] = 1. Select SPDIFO from pin 2 by
setting PCI 58h [1] = 1, and pin 2 must be configured as a multifunction pin (see pin 2 note).
Either pin 2 or pin 54 may be used for SPDIFO.
2
PCREQ#
PC/PCI request output. Enable PCREQ# by setting PCI 50h [10:8] = 010. Pin 53 is used as
PCREQ# when configured as an audio-only device. PCREQ# can only be used from pin 2
when the ES1988 is configured as a multifunction device (see pin 60 note). Pin 2 must be
configured as a multifunction pin (see pin 2 note).
(note)
Pin 2 is configured as a multifunction pin when pin 85 is pulled low. This will allow for
additional use of this pin for RO#, SPDIFO, or PCREQ#. If pin 85 is open or pulled high, then
pin 2 may only be used as IDSEL.
GND
3, 21, 40, 89
I
Digital ground.
AD[31:0]
4:11, 22:29,
31:38, 93:100
I/O
Address and data lines from the PCI bus.
VCC
12, 41, 90
I
Digital supply voltage, 3.3V.
Cycle frame.
FRAME#
IRDY#
14
15
16
17
18
19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Initiator ready.
Target ready.
TRDY#
DEVSEL#
STOP#
PAR
Device select.
Stop transaction.
Parity.
CLKRUN#
CLKRUN#, is I/O pin for PCI Clock status and an output to start or accelerate clock function
by enabling PCI 52h [11] = 1.
39
ECS
O
Chip select output to EEPROM chip select input. ECS is active after power-on reset and
goes inactive automatically after EEPROM cycle is complete.
GD[0]
42
43
I/O
I/O
O
Game port data input/output.
Game port data input/output.
GD[1]
EDOUT
Data output to EEPROM data input. EDOUT goes active after power-on reset and goes
inactive automatically after EEPROM cycle is complete.
ESS Technology, Inc.
SAM0368-051302
3
ESS [ ESS Technology,Inc ]
