ESMT
M24L16161ZA
Variable Address Mode Register (VAR) Update[5, 6]
Deep Sleep Mode—Entry/Exit[7]
VAR Update and Deep Sleep Mode Timing[5, 6]
Parameter
tZZWE
Description
ZZ LOW to Write Start
Min.
Max.
Unit
1
µs
tCDR
0
ns
Chip deselect to ZZ LOW
tR[7]
Operation Recovery Time (Deep Sleep Mode only)
Deep Sleep Mode Time
200
8
µs
µs
tZZMIN
Notes:
5. OE and the data pins are in a don’t care state while the device is in variable address mode.
6. All other timing parameters are as shown in the data sheets.
7. tR applies only in the deep sleep mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0 4/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
