ESMT
M24L16161ZA
Switching Characteristics Over the Operating Range [12, 13, 14, 15, 18]
-70
Parameter
Read Cycle
Description
Unit
Min.
Max.
tRC[17]
tCD
Read Cycle Time
Chip Deselect Time
70
15
40000
ns
ns
CE , BLE /BHE High Pulse Time
Address to Data Valid
Data Hold from Address Change
tAA
tOHA
tACE
70
ns
ns
ns
5
70
35
CE LOW to Data Valid
tDOE
ns
ns
ns
ns
ns
ns
ns
ns
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
5
OE LOW to Low Z[13, 14, 16]
OE HIGH to High Z[13, 14, 16]
CE LOW to Low Z[13, 14, 16]
CE HIGH to High Z[13, 14, 16]
BLE /BHE LOW to Data Valid
BLE /BHE LOW to Low Z[13, 14, 16]
BLE /BHE HIGH to High Z[13, 14, 16]
25
10
25
70
tLZBE
tHZBE
5
25
Write Cycle[15]
tWC
Write Cycle Time
70
60
60
40000
ns
ns
tSCE
tAW
CE LOW to Write End
Address Set-Up to Write End
ns
ns
Chip Deselect Time CE , BLE / BHE High Pulse
Time
tCD
15
tHA
tSA
tPWE
Address Hold from Write End
Address Set-Up to Write Start
0
0
50
ns
ns
ns
WE Pulse Width
tBW
60
ns
BLE /BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
tSD
tHD
tHZWE
25
0
ns
ns
ns
25
WE LOW to High-Z[13, 14, 16]
WE HIGH to Low-Z[13, 14, 16]
tLZWE
10
ns
Notes:
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and
Waveforms” section.
13. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and
tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates the write.
16. High-Z and Low-Z parameters are characterized and are not 100% tested.
17. If invalid address signals shorter than min. tRC are continuously repeated for 40 µs, the device needs a normal read timing
(tRC) or needs to enter standby state at least once in every 40 µs.18.In order to achieve 70-ns performance, the read access
must be CE controlled. That is, the addresses must be stable prior to CE going active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0 9/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
