ESMT
M24L16161ZA
PSRAM
16-Mbit (1M x 16)
Pseudo Static RAM
are disabled ( OE HIGH), both Byte High Enable and Byte
Low Enable are disabled ( BHE , BLE HIGH), or during a
write operation ( CE LOW and WE LOW).
Features
‧Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power— Typical active current: 3 mA @ f =
1 MHz— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Deep Sleep Mode
To write to the device, take Chip Enable ( CE LOW) and
Write Enable ( WE ) input LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written
into the location specified on the address pins (A0 through
A19). If Byte High Enable (BHE ) is LOW, then data from I/O
pins (I/O8 through I/O15) is written into the location specified
on the address pins (A0 through A19).
• Offered in a Lead-Free 48-ball BGA package
• Operating Temperature: –40°C to +85°C
To read from the device, take Chip Enables ( CE LOW) and
Output Enable ( OE ) LOW while forcing the Write Enable
Functional Description[1]
( WE ) HIGH. If Byte Low Enable (BLE ) is LOW, then data
from the memory location specified by the address pins will
The M24L16161ZA is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
appear on I/O0 to I/O7. If Byte High Enable (BHE ) is LOW,
then data from memory will appear on I/O8 to I/O15. Refer to
the Truth Table for a complete description of read and write
modes. To enable Deep Sleep Mode, drive ZZ LOW. See
the Truth Table for a complete description of Read, Write, and
Deep Sleep mode.
deselected ( OE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected ( OE HIGH), outputs
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
2/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
