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M14D5121632A-2.5BG2A 参数 Datasheet PDF下载

M14D5121632A-2.5BG2A图片预览
型号: M14D5121632A-2.5BG2A
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 64 页 / 1089 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2A)  
Operation Temperature Condition  
Parameter  
Symbol  
Value  
Unit  
Operation temperature  
TC  
0 ~ +95  
°C  
Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.  
2. Supporting 0 to +85with full AC and DC specifications.  
Supporting 0 to + 85and being able to extend to + 95 with doubling auto-refresh commands in frequency to a  
32ms period ( tREFI = 3.9μ s ) and higher temperature Self-Refresh entry via A7 “1” on EMRS(2).  
DC Operation Condition & Specifications  
DC Operation Condition  
(Recommended DC operating conditions)  
Parameter  
Supply voltage  
Symbol  
Min.  
Typ.  
Max.  
Unit Note  
VDD  
VDDL  
1.7  
1.7  
1.8  
1.9  
V
V
V
V
V
V
V
4,9  
4,9  
Supply voltage for DLL  
Supply voltage for output  
Input reference voltage  
1.8  
1.9  
VDDQ  
1.7  
1.8  
1.9  
4,9  
VREF  
0.49 x VDDQ  
VREF - 0.04  
VREF + 0.125  
-0.3  
0.5 x VDDQ  
0.51 x VDDQ  
VREF + 0.04  
VDDQ + 0.3  
VREF - 0.125  
1,2,9  
3,9  
Termination voltage (system)  
Input logic high voltage  
VTT  
VREF  
VIH (DC)  
VIL (DC)  
-
-
Input logic low voltage  
(All voltages referenced to VSS)  
Parameter  
Symbol  
VOH  
Value  
Unit  
V
Note  
Minimum required output pull-up under AC test load  
Maximum required output pull-down under AC test load  
Input leakage current  
VTT + 0.603  
8
8
VOL  
VTT - 0.603  
V
|I LI|  
5
5
uA  
uA  
mA  
5
Output leakage current  
|I LO  
|
6
Output minimum source DC current ( VDDQ(min); VOUT  
=1.42V )  
I OH  
7, 8  
-13.4  
Output minimum sink DC current ( VDDQ(min); VOUT  
0.28V )  
=
I OL  
mA  
7, 8  
+13.4  
Note:  
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of  
VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.  
2. Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).  
3. VTT of transmitting device must track VREF of receiving device.  
4. VDDQ and VDDL track VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together.  
5. Any input 0V VIN VDD; all other balls not under test = 0V.  
6. 0V VOUT VDDQ; DQ and ODT disabled.  
7. The DC value of VREF applied to the receiving device is expected to be set to VTT.  
8. After OCD calibration to 18at TC = 25, VDD = VDDQ = 1.8V  
9. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, under all conditions  
VDDQ must be less than or equal to VDD.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Oct. 2016  
Revision : 1.0 5/64