ESMT
M13S5121632A (2A)
AC Operating Test Conditions
Parameter
Input reference voltage for clock (VREF
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (VIH/VIL)
Value
Unit
V
)
0.5*VDDQ
1.5
V
1.0
V/ns
V
VREF+0.31/VREF-0.31
Input timing measurement reference level
Output timing reference level
VREF
VTT
V
V
AC Timing Parameter & Specifications
(VDD = 2.3V~2.7V, VDDQ= 2.3V~2.7V, TA =0°C ~ 70°C )
-4
-5
Unit
Note
Parameter
Symbol
min
max
13
min
7.5
6
max
13
CL2
CL2.5
CL3
7.5
6
Clock Period
tCK
ns
ns
13
13
4
10
5
10
tAC
-0.7
+0.7
-0.7
+0.7
Access time from CLK/ CLK
CLK high-level width
tCH
tCL
0.45
0.45
-0.6
0.72
0.5
0.55
0.55
+0.6
1.28
-
0.45
0.45
-0.6
0.72
0.5
0.55
0.55
+0.6
1.28
-
tCK
tCK
ns
tCK
ns
ns
CLK low-level width
Data strobe edge to clock edge
tDQSCK
tDQSS
tDS
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
tDH
0.5
-
0.5
-
DQ and DM input pulse width (for each
input)
tDIPW
1.75
-
1.75
-
ns
Input setup time
tIS
0.6
0.6
0.35
0.35
0.2
0.2
-
-
0.6
0.6
0.35
0.35
0.2
0.2
-
-
ns
ns
tCK
tCK
tCK
tCK
ns
5
5
Input hold time
tIH
-
-
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
tDQSH
tDQSL
tDSS
tDSH
tDQSQ
-
-
-
-
-
-
-
-
0.40
0.40
Data-out high-impedance window from
CLK/ CLK
tHZ
-0.7
-0.7
+0.7
+0.7
-0.7
-0.7
+0.7
+0.7
ns
ns
1
1
Data-out low-impedance window from
CLK/ CLK
tLZ
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2012
Revision : 1.1 6/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
