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M13S5121632A-5TG2A 参数 Datasheet PDF下载

M13S5121632A-5TG2A图片预览
型号: M13S5121632A-5TG2A
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 47 页 / 969 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S5121632A (2A)  
Absolute Maximum Rating  
Parameter  
Voltage on any pin relative to VSS  
Voltage on VDD supply relative to VSS  
Voltage on VDDQ supply relative to VSSQ  
Operating ambient temperature  
Storage temperature  
Symbol  
VIN, VOUT  
VDD  
Value  
-0.5 ~ VDDQ + 0.5  
-0.5 ~ 3.7  
Unit  
V
V
VDDQ  
-0.5 ~ 3.7  
V
°C  
TA  
0 ~ +70  
TSTG  
-55 ~ +150  
°C  
Power dissipation  
PD  
IOS  
1500  
50  
mW  
mA  
Short circuit current  
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommend operation condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
DC Operation Condition & Specifications  
DC Operation Condition  
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C )  
Parameter  
Symbol  
VDD  
Min  
2.3  
Max  
2.7  
Unit  
V
Note  
Supply voltage  
I/O Supply voltage  
VDDQ  
2.3  
2.7  
V
I/O Reference voltage  
VREF  
0.49*VDDQ  
VREF - 0.04  
VREF + 0.15  
-0.3  
0.51*VDDQ  
VREF + 0.04  
VDDQ + 0.3  
VREF - 0.15  
V
1
2
I/O Termination voltage (system)  
Input logic high voltage  
Input logic low voltage  
VTT  
V
VIH (DC)  
VIL (DC)  
VIN (DC)  
V
V
V
-0.3  
VDDQ + 0.3  
Input Voltage Level, CLK and CLK inputs  
VID (DC)  
0.36  
-2  
VDDQ + 0.6  
V
3
Input Differential Voltage, CLK and CLK inputs  
Input leakage current  
II  
μ A  
μ A  
2
5
Output leakage current  
IOZ  
-5  
Output High Current (Normal strength driver)  
(VOUT =VDDQ-0.373V, min VREF, min VTT)  
IOH  
IOL  
-16.2  
mA  
mA  
Output Low Current (Normal strength driver)  
(VOUT = 0.373V)  
+16.2  
Notes: 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.  
Peak-to-peak noise on VREF may not exceed 2% of the DC value.  
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal  
to VREF, and must track variations in the DC level of VREF  
.
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .  
Elite Semiconductor Memory Technology Inc.  
Publication Date : May 2012  
Revision : 1.1 4/47