ESMT
M13S2561616A
Operation Temperature Condition -40~85°C
Functional Block Diagram
CLK
Clock
Generator
CLK
Bank D
Bank C
Bank B
Row
Address
Address
Buffer
&
Refresh
Counter
Mode Register &
Extended Mode
Register
Bank A
Sense Amplifier
Column Decoder
DM
Column
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Data Control Circuit
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
x16
x1 6
VDD
DQ0
1
2
66
65
64
63
VSS
DQ15
VSS Q
DQ14
VDDQ
DQ1
DQ2
VSS Q
DQ3
DQ4
VDDQ
DQ5
DQ6
3
4
5
62
61
DQ13
VDDQ
DQ12
DQ11
VSS Q
DQ10
DQ9
6
7
60
59
58
57
56
55
54
53
52
51
8
9
10
11
66 PIN TSOP(II)
VSS Q
DQ7
12
13
14
15
VDDQ
DQ8
(400mil x 875mil)
NC
(0.65mm PIN PITCH)
NC
VSS Q
VDDQ
LDQS 16
UDQS
NC
17
18
19
20
50
49
NC
VDD
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
48
47
46
45
44
43
42
41
40
LDM
WE
21
22
CAS
RAS
23
CS
NC
24
25
26
27
A12
BA0
BA1
A11
A9
A10/AP 28
39
A8
A7
A6
A5
A4
VSS
A0
29
30
31
32
38
37
A1
A2
36
35
34
A3
VDD
33
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1 3/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
