ESMT
M13S128324A
Pin Arrangement
A
7
6
81
50
DQ29
VSSQ
82
83
84
A
49
48
A
A
V
A
5
DQ30
DQ31
4
47
46
VSS
85
86
SS
9
VDDQ
45
44
43
42
41
87
88
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
100 Pin LQFP
Forward Type
20 x 14 mm
89
90
40
39
91
92
93
94
95
VSSQ
N.C
N.C
A11
A10
0.65 mmpin Pitch
N.C
38
37
36
35
34
33
32
31
DQS
VDDQ
VDD
V
DD
96
97
98
99
100
A
3
DQ0
DQ1
A
2
1
VSSQ
A
DQ2
A0
Pin Description
(M13S128324A)
Pin Name
Function
Pin Name
Function
Address inputs
- Row address A0~A11
A0~A11,
BA0,BA1
- Column address A0~A7
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
DM0~DM3
DQ Mask enable in write cycle.
Clock input
DQ0~DQ31
Data-in/Data-out
CLK, CLK
CKE
Row address strobe
Column address strobe
Write enable
Clock enable
RAS
CAS
Chip select
CS
VDDQ
VSSQ
VREF
Supply Voltage for GDQ
Ground for DQ
WE
VSS
Ground
VDD
Power
Reference Voltage for SSTL
Bi- directional Data Strobe.
DQS0 correspond to the data on DQ0~DQ7.
DQS1 correspond to the data on DQ8~DQ15.
DQS2 correspond to the data on DQ16~DQ23.
DQS3 correspond to the data on DQ24~DQ31.
DQS0~DQS3
(for FBGA)
NC
-
No connection
DQS
-
Bi- directional Data Strobe.
(for LQFP)
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
4/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
