ESMT
M13S128324A
AC Timing Parameter & Specifications-continued
-3.6
-4(CL3)
-4
-5
-6
Symbol
Unit
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
t
CLmin
or
-
-
-
-
-
Half Clock Period
tHP
tQH
tRAS
tRC
ns
ns
tCHmin
tHP-0.
4
tHP-0.
45
tHP-0.
45
tHP-0.
45
tHP-0.
5
DQ-DQS output hold time
-
-
-
-
-
ACTIVE to PRECHARGE
command
120K
ns
120K
ns
120K
ns
120K
ns
120K
ns
11
16
18
10
15
17
10
15
17
8
7
tCK
tCK
tCK
Row Cycle Time
-
-
-
-
-
-
12
14
-
-
10
12
-
-
AUTO REFRESH Row Cycle
Time
tRFC
ACTIVE to READ,WRITE
delay
tRCD
tRP
5
4
-
-
5
4
-
-
5
4
-
-
4
4
-
-
3
3
-
-
tCK
tCK
PRECHARGE command
period
ACTIVE to READ with
AUTOPRECHARGE
command
tRAP
4
-
4
-
4
-
4
-
3
-
tCK
ACTIVE bank A to ACTIVE
bank B command
tRRD
tWR
3
15
2
-
-
-
3
15
2
-
-
-
3
15
2
-
-
-
2
15
2
-
-
-
2
15
2
-
-
-
tCK
ns
tCK
Write recovery time
Write data in to READ
command delay
tWTR
Col. Address to Col. Address
delay
tCCD
tREFI
1
-
-
1
-
-
1
-
-
1
-
-
1
-
-
tCK
us
Average periodic refresh
interval
7.8
7.8
7.8
7.8
7.8
Write preamble
tWPRE
tWPST
tRPRE
tRPST
0.25
0.4
-
0.25
0.4
-
0.25
0.4
-
0.25
0.4
-
0.25
0.4
-
tCK
tCK
tCK
tCK
Write postamble
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
0.6
DQS read preamble
DQS read postamble
0.9
0.9
0.9
0.9
0.9
0.4
0.4
0.4
0.4
0.4
Clock to DQS write preamble
setup time
tWPRES
0
2
-
-
0
2
-
-
0
2
-
-
0
2
-
-
0
2
-
-
ns
Load Mode Register /
Extended Mode register
cycle time
tMRD
tCK
Exit self refresh to READ
command
tXSRD
tXSNR
200
-
-
200
-
-
200
-
-
200
75
-
-
200
-
-
tCK
ns
Exit self refresh to
non-READ command
75
75
75
75
(tWR/tC
(tWR/tC
(tWR/tC
(tWR/tC
K) +
(tRP/tC
(tWR/tC
)
)
)
Autoprecharge write
recovery+Precharge time
K
K
K
)
K
tDAL
-
-
-
-
-
tCK
+(tRP/t
+(tRP/t
+(tRP/t
+(tRP/t
)
)
)
)
)
K
CK
CK
CK
CK
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8 8/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
