ESMT
M13S128168A
AC Operating Test Conditions
Parameter
Value
Unit
V
Input reference voltage for clock (VREF
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (VIH/VIL)
)
0.5*VDDQ
1.5
V
1.0
V/ns
V
VREF+0.31/VREF-0.31
Input timing measurement reference level
Output timing reference level
VREF
VTT
V
V
AC Timing Parameter & Specifications
(VDD = 2.375V~2.75V, VDDQ=2.375V~2.75V, TA =0°C to 70°C )(Note)
-5
-6
Symbol
Parameter
min
max
min
max
Clock Period
CL3
tCK
tAC
5.0
10
6.0
10
ns
ns
-0.7
+0.7
-0.7
+0.7
Access time from CLK/ CLK
CLK high-level width
tCH
tCL
0.45
0.45
-0.6
0.75
0.45
0.45
1.75
0.75
0.75
0.8
0.55
0.45
0.45
-0.6
0.75
0.45
0.45
1.75
0.75
0.75
0.8
0.55
tCK
tCK
ns
tCK
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
ns
CLK low-level width
0.55
0.55
Data strobe edge to clock edge
tDQSCK
tDQSS
tDS
+0.6
+0.6
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each input)
1.25
1.25
-
-
tDH
-
-
tDIPW
tIS
-
-
Input setup time (fast slew rate)
Input hold time (fast slew rate)
Input setup time (slow slew rate)
Input hold time (slow slew rate)
Control and Address input pulse width
DQS input high pulse width
-
-
tIH
-
-
tIS
-
-
tIH
0.8
-
-
0.8
-
-
tIPW
tDQSH
tDQSL
tDSS
tDSH
tDQSQ
2.2
2.2
0.4
0.6
0.6
-
0.4
0.6
0.6
-
DQS input low pulse width
0.4
0.4
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
0.2
0.2
0.2
-
0.2
-
-
0.45
-
0.45
Data-out high-impedance window from
CLK/ CLK
tHZ
-0.7
-0.7
+0.7
+0.7
-0.7
-0.7
+0.7
+0.7
ns
ns
Data-out low-impedance window from
CLK/ CLK
tLZ
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8 7/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
