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M12S64164A 参数 Datasheet PDF下载

M12S64164A图片预览
型号: M12S64164A
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位×4银行同步DRAM [1M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 45 页 / 1058 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12S64164A  
AC CHARACTERISTICS (AC operating condition unless otherwise noted)  
-6  
-7  
-10  
PARAMATER  
CAS latency = 3  
SYMBOL  
UNIT NOTE  
MIN  
6
MAX  
MIN  
7
MAX  
MIN  
10  
MAX  
CLK cycle time  
tCC  
1000  
1000  
1000  
ns  
ns  
ns  
1
1,2  
2
CAS latency = 2  
CAS latency = 3  
CAS latency = 2  
CAS latency = 3  
CAS latency = 2  
10  
10  
12  
5.5  
6
6
6
7
8
CLK to valid  
output delay  
tSAC  
2.5  
2.5  
2.5  
2.5  
1.5  
1
2.5  
2.5  
2.5  
2.5  
1.5  
1
2.5  
2.5  
3
Output data  
hold time  
tOH  
CLK high pulse width  
CLK low pulse width  
Input setup time  
tCH  
tCL  
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
3
tSS  
tSH  
tSLZ  
2.5  
1.5  
0
Input hold time  
CLK to output in Low-Z  
0
0
CAS latency = 3  
CAS latency = 2  
5.5  
6
6
6
7
8
CLK to output  
in Hi-Z  
tSHZ  
ns  
-
Note:  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.  
3. Assumed input rise and fall time (tr & tf) =1ns.  
If tr & tf is longer than 1ns. transient time compensation should be considered.  
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Apr. 2009  
Revision: 1.2 6/45