ESMT
M12S64164A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 °C
VERSION
PARAMETER
SYMBOL
TEST CONDITION
UNIT NOTE
-6
-7
-10
Burst Length = 1, tRC ≥ tRC(min), IOL = 0 mA,
tcc = tcc(min)
Operating Current
(One Bank Active)
ICC1
85
85
60
mA
mA
1,2
ICC2P
2
1
CKE ≤ VIL(max), tcc = tcc(min)
CKE & CLK ≤ VIL(max), tcc = ∞
Precharge Standby Current
in power-down mode
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = tcc(min)
Input signals are changed one time during 2CLK
ICC2N
20
10
Precharge Standby Current
in non power-down mode
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
ICC2NS
ICC3P
10
10
CKE ≤ VIL(max), tcc = tcc(min)
Active Standby Current
in power-down mode
mA
mA
ICC3PS
CKE & CLK ≤ VIL(max), tcc = ∞
CS CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 15ns
ICC3N
30
Input signals are changed one time during 2 CLKs
All other pins ≥ VDD - 0.2V or ≤ 0.2V
Active Standby Current
in non power-down mode
(One Bank Active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
ICC3NS
25
mA
mA
Operating Current
(Burst Mode)
IOL = 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
tRFC ≥ tRFC(min), tCC = tcc(min)
ICC4
1,2
150
150
140
120
120
Refresh Current
ICC5
ICC6
140
1
mA
mA
Self Refresh Current
CKE ≤ 0.2V
Note:
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 4/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
