ESMT
M12L64322A (2U)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C )
Parameter
Input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall-time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
Vtt = 1.4V
3.3V
50 Ω
1200
Ω
VOH (DC) =2.4V , IOH = -2 mA
VOL (DC) =0.4V , IOL = 2 mA
Output
Output
Z0 =50 Ω
30pF
30pF
870 Ω
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-5
-6
-7
Row active to row active delay
tRRD(min)
tRCD(min)
10
12
14
ns
ns
1
1
15
18
20
RAS to CAS delay
Row precharge time
tRP(min)
15
40
18
42
100
60
1
20
42
ns
ns
1
1
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
Row active time
us
Row cycle time
@ Operating
55
63
ns
1
2
2
2
3
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
CLK
CLK
CLK
CLK
2
1
Col. address to col. address delay
1
CAS latency = 3
CAS latency = 2
2
Number of valid
Output data
ea
4
1
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0 6/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
